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Searched refs:backend_instruction (Results 1 – 19 of 19) sorted by relevance

/third_party/mesa3d/src/intel/compiler/
Dbrw_cfg.h95 backend_instruction *start();
96 const backend_instruction *start() const;
97 backend_instruction *end();
98 const backend_instruction *end() const;
108 backend_instruction *first_non_control_flow_inst();
109 backend_instruction *last_non_control_flow_inst();
129 static inline struct backend_instruction *
132 return (struct backend_instruction *)exec_list_get_head(&block->instructions); in bblock_start()
135 static inline const struct backend_instruction *
138 return (const struct backend_instruction *)exec_list_get_head_const(&block->instructions); in bblock_start_const()
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Dbrw_dead_control_flow.cpp51 backend_instruction *const inst = block->start(); in dead_control_flow_eliminate()
52 backend_instruction *const prev_inst = prev_block->end(); in dead_control_flow_eliminate()
60 backend_instruction *const else_inst = prev_inst; in dead_control_flow_eliminate()
68 backend_instruction *const endif_inst = inst; in dead_control_flow_eliminate()
69 backend_instruction *const if_inst = prev_inst; in dead_control_flow_eliminate()
104 backend_instruction *const if_inst = prev_inst; in dead_control_flow_eliminate()
105 backend_instruction *const else_inst = inst; in dead_control_flow_eliminate()
Dbrw_shader.cpp861 backend_instruction::is_commutative() const in is_commutative()
885 backend_instruction::is_3src(const struct brw_compiler *compiler) const in is_3src()
891 backend_instruction::is_tex() const in is_tex()
912 backend_instruction::is_math() const in is_math()
927 backend_instruction::is_control_flow() const in is_control_flow()
944 backend_instruction::uses_indirect_addressing() const in uses_indirect_addressing()
957 backend_instruction::can_do_source_mods() const in can_do_source_mods()
985 backend_instruction::can_do_saturate() const in can_do_saturate()
1032 backend_instruction::can_do_cmod() const in can_do_cmod()
1079 backend_instruction::reads_accumulator_implicitly() const in reads_accumulator_implicitly()
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Dbrw_schedule_instructions.cpp66 schedule_node(backend_instruction *inst, instruction_scheduler *sched);
71 backend_instruction *inst;
671 virtual int issue_time(backend_instruction *inst) = 0;
673 virtual void count_reads_remaining(backend_instruction *inst) = 0;
675 virtual void update_register_pressure(backend_instruction *inst) = 0;
676 virtual int get_register_pressure_benefit(backend_instruction *inst) = 0;
744 int issue_time(backend_instruction *inst);
747 void count_reads_remaining(backend_instruction *inst);
749 void update_register_pressure(backend_instruction *inst);
750 int get_register_pressure_benefit(backend_instruction *inst);
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Dbrw_predicated_break.cpp111 backend_instruction *const do_inst = block->start(); in opt_predicated_break()
116 backend_instruction *jump_inst = block->end(); in opt_predicated_break()
133 backend_instruction *if_inst = block->prev()->end(); in opt_predicated_break()
137 backend_instruction *endif_inst = block->next()->start(); in opt_predicated_break()
190 backend_instruction *while_inst = while_block->start(); in opt_predicated_break()
Dbrw_ir.h92 struct backend_instruction : public exec_node { struct
111 void insert_after(bblock_t *block, backend_instruction *inst);
112 void insert_before(bblock_t *block, backend_instruction *inst);
128 struct backend_instruction {
Dbrw_disasm_info.h34 struct backend_instruction;
80 struct backend_instruction *inst, unsigned offset);
Dbrw_shader.h85 virtual void dump_instruction(const backend_instruction *inst) const = 0;
86 virtual void dump_instruction(const backend_instruction *inst, FILE *file) const = 0;
Dbrw_cfg.cpp108 ends_block(const backend_instruction *inst) in ends_block()
121 starts_block(const backend_instruction *inst) in starts_block()
162 foreach_inst_in_block(backend_instruction, inst, this) { in dump()
191 foreach_in_list_safe(backend_instruction, inst, instructions) { in cfg_t()
Dbrw_vec4.h287 void dump_instruction(const backend_instruction *inst) const;
288 void dump_instruction(const backend_instruction *inst, FILE *file) const;
Dbrw_ir_performance.cpp1327 const backend_instruction *inst, in accum_reg_of_channel()
1342 const backend_instruction *be_inst) in issue_fs_inst()
1463 const backend_instruction *be_inst) in issue_vec4_instruction()
1575 const backend_instruction *), in calculate_performance() argument
1613 foreach_inst_in_block(backend_instruction, inst, block) { in calculate_performance()
Dbrw_disasm_info.c130 struct backend_instruction *inst, unsigned offset) in disasm_annotate()
Dbrw_fs.h348 void dump_instruction(const backend_instruction *inst) const;
349 void dump_instruction(const backend_instruction *inst, FILE *file) const;
Dbrw_fs_register_coalesce.cpp331 foreach_block_and_inst_safe (block, backend_instruction, inst, cfg) { in register_coalesce()
Dbrw_ir_vec4.h269 class vec4_instruction : public backend_instruction {
Dbrw_vec4.cpp245 if (!backend_instruction::can_do_source_mods()) in can_do_source_mods()
254 if (!backend_instruction::can_do_cmod()) in can_do_cmod()
1306 vec4_visitor::dump_instruction(const backend_instruction *be_inst) const in dump_instruction()
1312 vec4_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) const in dump_instruction()
Dbrw_ir_fs.h328 class fs_inst : public backend_instruction {
Dbrw_fs.cpp447 if (!backend_instruction::can_do_source_mods()) in can_do_source_mods()
456 if (!backend_instruction::can_do_cmod()) in can_do_cmod()
5622 foreach_block_and_inst(block, backend_instruction, inst, cfg) { in dump_instructions()
5631 foreach_in_list(backend_instruction, inst, &instructions) { in dump_instructions()
5643 fs_visitor::dump_instruction(const backend_instruction *be_inst) const in dump_instruction()
5649 fs_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) const in dump_instruction()
/third_party/mesa3d/docs/relnotes/
D21.2.0.rst2733 - intel/compiler: Add the ability to defer IP updates in backend_instruction::remove