| /third_party/mesa3d/src/amd/addrlib/src/r800/ |
| D | egbaddrlib.cpp | 945 macroTileHeight = MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks / in ComputeSurfaceAlignmentsMacroTiled()
955 pipes * pTileInfo->bankWidth * pTileInfo->banks * pTileInfo->bankHeight * tileSize; in ComputeSurfaceAlignmentsMacroTiled()
980 switch (pTileInfo->banks) in SanityCheckMacroTiled()
1040 if (pTileInfo->banks < pTileInfo->macroAspectRatio) in SanityCheckMacroTiled()
1063 ADDR_ASSERT(numPipes * pTileInfo->banks >= 4); in SanityCheckMacroTiled()
1494 (MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks) / in ComputeMacroTileEquation()
1641 UINT_32 numBankBits = Log2(pTileInfo->banks); in ComputeSurfaceAddrFromCoordMacroTiled()
1735 (MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks) / pTileInfo->macroAspectRatio; in ComputeSurfaceAddrFromCoordMacroTiled()
1743 (numPipes * pTileInfo->banks); in ComputeSurfaceAddrFromCoordMacroTiled()
2352 UINT_32 banks = pTileInfo->banks; in ComputeSurfaceCoordFromAddrMacroTiled() local
[all …]
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| D | ciaddrlib.cpp | 241 pOut->dccRamBaseAlign = pIn->tileInfo.banks * in HwlComputeDccInfo()
299 UINT_32 numOfBanks = pIn->pTileInfo->banks; in HwlComputeCmaskAddrFromCoord()
343 UINT_32 numOfBanks = pIn->pTileInfo->banks; in HwlComputeHtileAddrFromCoord()
611 pInfo->banks = 2; in HwlSetupTileCfg()
966 tileInfo.banks * tileInfo.bankWidth * in HwlOptimizeTileMode()
1490 HwlGetPipes(&tileInfo) * tileInfo.banks * in HwlSetupTileInfo()
1501 HwlGetPipes(&tileInfo) * tileInfo.banks * in HwlSetupTileInfo()
1645 pCfg->info.banks = 2; in ReadGbTileMode()
1741 pCfg->banks = 1 << (gbTileMode.f.alt_num_banks + 1); in ReadGbMacroTileCfg()
1747 pCfg->banks = 1 << (gbTileMode.f.num_banks + 1); in ReadGbMacroTileCfg()
[all …]
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| D | siaddrlib.cpp | 247 switch (pTileInfo->banks) in ComputeBankEquation()
2523 UINT_32 yBitToCheck = QLog2(pTileInfo->banks) - 1; in HwlComputeSurfaceCoord2DFromBankPipe()
3019 pInfo->banks = 2; in HwlSetupTileCfg()
3083 pCfg->info.banks = 1 << (gbTileMode.f.num_banks + 1); in ReadGbTileMode()
3527 UINT_32 baseAlign = tileSize * pipes * m_tileTable[i].info.banks * in HwlComputeMaxBaseAlignments()
3655 key.fields.numBanksLog2 = Log2(tileConfig.info.banks); in InitEquationTable()
3721 MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks / in InitEquationTable()
3800 MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks / in InitEquationTable()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_fs_bank_conflicts.cpp | 819 weight_vector_type *banks = new weight_vector_type[4]; in bank_characteristics() local
822 banks[b] = weight_vector_type(2 * map.size); in bank_characteristics()
826 set(banks[b], j, p, in bank_characteristics()
831 return banks; in bank_characteristics()
849 weight_vector_type *banks = bank_characteristics(map); in optimize_reg_permutation() local
865 delta_conflicts(banks[bank_r], banks[bank_s], conflicts[r]) + in optimize_reg_permutation()
866 delta_conflicts(banks[bank_s], banks[bank_r], conflicts[s]); in optimize_reg_permutation()
878 swap(banks[b], r, p, best_s, p); in optimize_reg_permutation()
886 delete[] banks; in optimize_reg_permutation()
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| /third_party/node/deps/brotli/c/enc/ |
| D | hash_forgetful_chain_inc.h | 136 FN(Bank)* BROTLI_RESTRICT banks = FN(Banks)(self->extra); in FN()
143 banks[bank].slots[idx].delta = (uint16_t)delta; in FN()
144 banks[bank].slots[idx].next = head[key]; in FN()
202 FN(Bank)* BROTLI_RESTRICT banks = FN(Banks)(self->extra); in FN()
254 slot = banks[bank].slots[last].next; in FN()
255 delta = banks[bank].slots[last].delta; in FN()
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| /third_party/skia/third_party/externals/brotli/c/enc/ |
| D | hash_forgetful_chain_inc.h | 136 FN(Bank)* BROTLI_RESTRICT banks = FN(Banks)(self->extra); in FN()
143 banks[bank].slots[idx].delta = (uint16_t)delta; in FN()
144 banks[bank].slots[idx].next = head[key]; in FN()
202 FN(Bank)* BROTLI_RESTRICT banks = FN(Banks)(self->extra); in FN()
254 slot = banks[bank].slots[last].next; in FN()
255 delta = banks[bank].slots[last].delta; in FN()
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| /third_party/mesa3d/src/freedreno/afuc/ |
| D | README.rst | 212 Many registers that are updated frequently have two banks, so they can be
213 updated without stalling for previous draw to finish. These banks are
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| /third_party/mesa3d/docs/relnotes/ |
| D | 18.1.1.rst | 38 - i965/glk: Add l3 banks count for 2x6 configuration
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| D | 18.0.5.rst | 62 - i965/glk: Add l3 banks count for 2x6 configuration
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| /third_party/skia/third_party/externals/angle2/extensions/ |
| D | EGL_CHROMIUM_sync_control.txt | 97 hardware register that swaps memory banks has been written). For pixel
|
| /third_party/flutter/skia/third_party/externals/angle2/extensions/ |
| D | EGL_CHROMIUM_get_sync_values.txt | 98 hardware register that swaps memory banks has been written). For pixel
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | GenericOpcodes.td | 898 // register banks have been selected.
907 // register banks have been selected.
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| /third_party/skia/third_party/externals/opengl-registry/extensions/OML/ |
| D | GLX_OML_sync_control.txt | 161 hardware register that swaps memory banks has been written). For pixel
|
| D | WGL_OML_sync_control.txt | 144 hardware register that swaps memory banks has been written). For pixel
|
| /third_party/openGLES/extensions/OML/ |
| D | GLX_OML_sync_control.txt | 161 hardware register that swaps memory banks has been written). For pixel
|
| D | WGL_OML_sync_control.txt | 144 hardware register that swaps memory banks has been written). For pixel
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| /third_party/mesa3d/src/amd/addrlib/src/core/ |
| D | addrlib1.cpp | 1290 …const UINT_32 align = HwlGetPipes(pIn->pTileInfo) * pIn->pTileInfo->banks * m_pipeInterleaveBy… in ComputeHtileInfo()
1925 baseAlign *= pTileInfo->banks; in ComputeCmaskBaseAlign()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 28 // We have banks of 32 registers each.
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| /third_party/openGLES/extensions/NV/ |
| D | NV_fence.txt | 114 dynamic data to all banks dedicated to dynamic data, and still
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| /third_party/skia/third_party/externals/opengl-registry/extensions/NV/ |
| D | NV_fence.txt | 114 dynamic data to all banks dedicated to dynamic data, and still
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPU.td | 221 "The number of LDS banks per compute unit."
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| /third_party/gstreamer/gstreamer/docs/random/uraeus/ |
| D | gstreamer_and_midi.txt | 18 filter banks implemented as software applications).
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| /third_party/mesa3d/src/amd/addrlib/inc/ |
| D | addrinterface.h | 453 UINT_32 banks; ///< Number of banks, numerical value member
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_surface.c | 918 surf->u.legacy.num_banks = csio->pTileInfo->banks; in gfx6_surface_settings()
1175 AddrTileInfoIn.banks = surf->u.legacy.num_banks; in gfx6_compute_surface()
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| /third_party/rust/crates/memchr/bench/data/opensubtitles/ |
| D | en-medium.txt | 173 I thought he favoured stage lines and banks.
1594 I thought he favoured stage lines and banks.
|