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Searched refs:base_reg (Results 1 – 11 of 11) sorted by relevance

/third_party/mesa3d/src/util/
Dregister_allocate.h62 unsigned int base_reg, unsigned int reg);
66 unsigned int base_reg, unsigned int reg0, unsigned int reg1);
Dregister_allocate.c160 unsigned int base_reg, unsigned int reg) in ra_add_transitive_reg_conflict() argument
162 ra_add_reg_conflict(regs, reg, base_reg); in ra_add_transitive_reg_conflict()
164 util_dynarray_foreach(&regs->regs[base_reg].conflict_list, unsigned int, in ra_add_transitive_reg_conflict()
179 unsigned int base_reg, unsigned int reg0, unsigned int reg1) in ra_add_transitive_reg_pair_conflict() argument
181 ra_add_reg_conflict(regs, reg0, base_reg); in ra_add_transitive_reg_pair_conflict()
182 ra_add_reg_conflict(regs, reg1, base_reg); in ra_add_transitive_reg_pair_conflict()
184 util_dynarray_foreach(&regs->regs[base_reg].conflict_list, unsigned int, i) { in ra_add_transitive_reg_pair_conflict()
/third_party/mesa3d/src/freedreno/ir3/
Dir3_spill.c128 struct ir3_register *base_reg; member
164 ctx->base_reg = mov->dsts[0]; in add_base_reg()
170 ctx->limit_pressure.full -= reg_size(ctx->base_reg); in add_base_reg()
746 ir3_src_create(spill, INVALID_REG, ctx->base_reg->flags)->def = ctx->base_reg; in spill()
920 ir3_src_create(reload, INVALID_REG, ctx->base_reg->flags)->def = ctx->base_reg; in reload()
1841 instr->dsts[0] == ctx->base_reg) in handle_block()
/third_party/mesa3d/src/amd/vulkan/
Dradv_cmd_buffer.c990 uint32_t base_reg = pipeline->user_data_0[stage]; in radv_emit_userdata_address() local
996 radv_emit_shader_pointer(device, cs, base_reg + loc->sgpr_idx * 4, va, false); in radv_emit_userdata_address()
1211 uint32_t base_reg = pipeline->user_data_0[stage]; in radv_emit_inline_push_consts() local
1217 radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, loc->num_sgprs); in radv_emit_inline_push_consts()
3299 uint32_t base_reg = cmd_buffer->state.graphics_pipeline->base.user_data_0[MESA_SHADER_VERTEX]; in emit_prolog_inputs() local
3302 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, in emit_prolog_inputs()
3890 uint32_t base_reg; in radv_emit_streamout_buffers() local
3900 base_reg = pipeline->base.user_data_0[stage]; in radv_emit_streamout_buffers()
3902 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, va, in radv_emit_streamout_buffers()
3909 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0; in radv_emit_streamout_buffers()
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/third_party/mesa3d/src/freedreno/decode/
Dcffdec.c1457 const unsigned base_reg = stage == MESA_SHADER_COMPUTE in cp_load_state() local
1462 const unsigned reg = base_reg + (dwords[1] >> 28) * 2; in cp_load_state()
1466 const unsigned reg = base_reg + (dwords[1] >> 28); in cp_load_state()
/third_party/mesa3d/src/microsoft/vulkan/
Ddzn_private.h660 uint32_t *base_reg; member
Ddzn_pipeline.c294 binding = layout->binding_translation[set].base_reg[binding]; in adjust_resource_index_binding()
325 var->data.binding = layout->binding_translation[s].base_reg[b]; in adjust_var_bindings()
Ddzn_descriptor_set.c578 layout->binding_translation[s].base_reg = binding_translation; in dzn_pipeline_layout_create()
591 uint32_t *binding_trans = layout->binding_translation[j].base_reg; in dzn_pipeline_layout_create()
/third_party/pcre2/pcre2/src/
Dpcre2_jit_simd_inc.h1142 sljit_s32 base_reg, sljit_s32 index_reg) in load_from_mem_vector() argument
1147 instruction[1] = (sljit_u16)(base_reg << 12); in load_from_mem_vector()
Dpcre2_jit_compile.c2613 int from_sp, base_reg, offset, i; in copy_recurse_data() local
2626 base_reg = STACK_TOP; in copy_recurse_data()
2633 base_reg = STACK_TOP; in copy_recurse_data()
2639 base_reg = TMP2; in copy_recurse_data()
2649 if (base_reg != TMP2) in copy_recurse_data()
2676 delayed_mem_copy_move(&status, base_reg, stackptr, SLJIT_SP, common->recursive_head_ptr); in copy_recurse_data()
2679 delayed_mem_copy_move(&status, SLJIT_SP, common->recursive_head_ptr, base_reg, stackptr); in copy_recurse_data()
2688 delayed_mem_copy_move(&status, base_reg, stackptr, SLJIT_SP, common->control_head_ptr); in copy_recurse_data()
2691 delayed_mem_copy_move(&status, SLJIT_SP, common->control_head_ptr, base_reg, stackptr); in copy_recurse_data()
2980 delayed_mem_copy_move(&status, base_reg, stackptr, SLJIT_SP, private_srcw[i]); in copy_recurse_data()
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/third_party/pcre2/pcre2/src/sljit/
DsljitNativeARM_32.c1012 #define EMIT_DATA_TRANSFER(type, add, target_reg, base_reg, arg) \ argument
1013 …(data_transfer_insts[(type) & 0xf] | ((add) << 23) | RD(target_reg) | RN(base_reg) | (sljit_uw)(ar…