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Searched refs:cmask_offset (Results 1 – 11 of 11) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_clear.c785 tex->surface.cmask_offset, tex->surface.cmask_size, 0xCCCCCCCC); in si_fast_clear()
820 uint64_t cmask_offset = 0; in si_fast_clear() local
837 … cmask_offset = tex->surface.cmask_offset + tex->surface.u.gfx9.color.cmask_level0.offset; in si_fast_clear()
841 cmask_offset = tex->surface.cmask_offset; in si_fast_clear()
857 cmask_offset = tex->surface.cmask_offset; in si_fast_clear()
864 cmask_offset = tex->surface.cmask_offset; in si_fast_clear()
871 cmask_offset, clear_size, 0); in si_fast_clear()
Dsi_texture.c485 tex->surface.cmask_offset = new_tex->surface.cmask_offset; in si_reallocate_texture_inplace()
1015 if (tex->surface.cmask_offset) { in si_texture_create_object()
1062 tex->surface.cmask_offset, tex->surface.cmask_size, in si_texture_create_object()
1147 tex->cmask_base_address_reg = (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8; in si_texture_create_object()
1815 tex->cmask_base_address_reg = (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8; in si_texture_invalidate_storage()
/third_party/mesa3d/src/amd/vulkan/
Dradv_meta_fmask_copy.c233 src_image->planes[0].surface.cmask_offset && in radv_fixup_copy_dst_metadata()
235 dst_image->planes[0].surface.cmask_offset); in radv_fixup_copy_dst_metadata()
Dradv_image.c1099 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.cmask_offset; in gfx10_make_texture_descriptor()
1301 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.cmask_offset; in si_make_texture_descriptor()
1316 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.cmask_offset; in si_make_texture_descriptor()
1419 if (!surf->cmask_size || surf->cmask_offset || surf->bpe > 8 || image->info.levels > 1 || in radv_image_alloc_single_sample_cmask()
1427 surf->cmask_offset = align64(surf->total_size, 1 << surf->cmask_alignment_log2); in radv_image_alloc_single_sample_cmask()
1428 surf->total_size = surf->cmask_offset + surf->cmask_size; in radv_image_alloc_single_sample_cmask()
Dradv_private.h2428 return image->planes[0].surface.cmask_offset; in radv_image_has_cmask()
Dradv_meta_clear.c1262 uint64_t offset = image->bindings[0].offset + image->planes[0].surface.cmask_offset; in radv_clear_cmask()
Dradv_device.c6327 va += surf->cmask_offset; in radv_initialise_color_surface()
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_surface.c450 surf_ws->cmask_offset = align64(surf_ws->total_size, 1 << surf_ws->cmask_alignment_log2); in radeon_winsys_surface_init()
451 surf_ws->total_size = surf_ws->cmask_offset + surf_ws->cmask_size; in radeon_winsys_surface_init()
/third_party/mesa3d/src/amd/common/
Dac_surface.c2510 surf->meta_offset = surf->display_dcc_offset = surf->fmask_offset = surf->cmask_offset = 0; in ac_compute_surface()
2521 surf->cmask_offset = align64(surf->total_size, 1 << surf->cmask_alignment_log2); in ac_compute_surface()
2522 surf->total_size = surf->cmask_offset + surf->cmask_size; in ac_compute_surface()
2559 if (!surf->fmask_offset && !surf->cmask_offset) { in ac_surface_zero_dcc_fields()
2946 if (surf->cmask_offset) in ac_surface_override_offset_stride()
2947 surf->cmask_offset += offset; in ac_surface_override_offset_stride()
3048 if (surf->cmask_offset) in ac_surface_print_info()
3052 surf->cmask_offset, surf->cmask_size, in ac_surface_print_info()
3101 if (surf->cmask_offset) in ac_surface_print_info()
3105 surf->cmask_offset, surf->cmask_size, in ac_surface_print_info()
Dac_surface.h381 uint64_t cmask_offset; member
Dac_surface_modifier_test.c258 assert(surf.cmask_offset == 0); in test_modifier()