Searched refs:conf_win_top_offset (Results 1 – 16 of 16) sorted by relevance
243 uint32_t conf_win_top_offset; member
273 uint32_t conf_win_top_offset; member
67 enc->enc_pic.crop_top = pic->seq.conf_win_top_offset; in radeon_uvd_enc_get_param()
127 enc->enc_pic.crop_top = pic->seq.conf_win_top_offset; in radeon_vcn_enc_get_param()
354 uint32_t conf_win_top_offset; member
276 context->desc.h265enc.seq.conf_win_top_offset = vl_rbsp_ue(rbsp); in parseEncSpsParamsH265()
476 uint16_t conf_win_top_offset; member
265 uint16_t conf_win_top_offset; member
827 ue(conf_win_top_offset, 0, current->pic_height_in_luma_samples); in FUNC()832 infer(conf_win_top_offset, 0); in FUNC()
398 sps->conf_win_top_offset = 0; in vaapi_encode_h265_init_sequence_params()
1121 guint32 conf_win_top_offset; member
1872 READ_UE (&nr, sps->conf_win_top_offset); in gst_h265_parse_sps()2062 (sps->conf_win_top_offset + sps->conf_win_bottom_offset) * crop_unit_y; in gst_h265_parse_sps()2064 sps->crop_rect_y = sps->conf_win_top_offset * crop_unit_y; in gst_h265_parse_sps()
8830 uint32_t conf_win_top_offset; member
832 deUint32 conf_win_top_offset; member
16949 s << "\tconf_win_top_offset = " << value.conf_win_top_offset << '\n';