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Searched refs:cr0 (Results 1 – 22 of 22) sorted by relevance

/third_party/mesa3d/src/intel/tools/tests/gen9/
Dcr0.asm1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
/third_party/mesa3d/src/intel/tools/tests/gen8/
Dcr0.asm1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
/third_party/mesa3d/src/intel/tools/tests/gen11/
Dcr0.asm1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
5 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
6 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
7 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000080UD { align1 1N switch };
/third_party/skia/third_party/externals/angle2/
DDEPS1736 'version': 'version:2@1.1.1.cr0',
1747 'version': 'version:2@1.1.1.cr0',
1758 'version': 'version:2@1.1.1.cr0',
1769 'version': 'version:2@1.1.1.cr0',
1780 'version': 'version:2@1.1.1.cr0',
1791 'version': 'version:2@1.1.1.cr0',
1802 'version': 'version:2@1.1.1.cr0',
1813 'version': 'version:2@1.1.1.cr0',
1824 'version': 'version:2@3.1.cr0',
1835 'version': 'version:2@1.1-alpha-2.cr0',
[all …]
/third_party/skia/gm/
Doffsetimagefilter.cpp156 SkIRect cr0 = SkIRect::MakeWH(40, 40); in onDraw() local
159 const SkRect r = SkRect::Make(cr0); in onDraw()
171 this->doDraw(canvas, r, SkImageFilters::Offset(20, 20, nullptr, &cr0), &cr0); in onDraw()
192 this->doDraw(canvas, r, SkImageFilters::Offset(40, 0, nullptr, &cr0), &cr0, &r); in onDraw()
196 this->doDraw(canvas, r, SkImageFilters::Offset(40, 0, nullptr, &cr0), &cr0, &r2); in onDraw()
/third_party/flutter/skia/gm/
Doffsetimagefilter.cpp158 SkIRect cr0 = SkIRect::MakeWH(40, 40); in onDraw() local
161 const SkRect r = SkRect::Make(cr0); in onDraw()
173 this->doDraw(canvas, r, SkImageFilters::Offset(20, 20, nullptr, &cr0)); in onDraw()
194 this->doDraw(canvas, r, SkImageFilters::Offset(40, 0, nullptr, &cr0), &r); in onDraw()
198 this->doDraw(canvas, r, SkImageFilters::Offset(40, 0, nullptr, &cr0), &r2); in onDraw()
/third_party/libjpeg-turbo/simd/powerpc/
Djccolext-altivec.c48 __vector int y0, y1, y2, y3, cr0, cr1, cr2, cr3, cb0, cb1, cb2, cb3; in jsimd_rgb_ycc_convert_altivec() local
249 cr0 = vec_msums(bg0, pw_mf008_mf041, pd_onehalfm1_cj); in jsimd_rgb_ycc_convert_altivec()
253 cr0 = (__vector int)vec_msum((__vector unsigned short)rg0, pw_f050_f000, in jsimd_rgb_ycc_convert_altivec()
254 (__vector unsigned int)cr0); in jsimd_rgb_ycc_convert_altivec()
261 crl = vec_perm((__vector unsigned short)cr0, in jsimd_rgb_ycc_convert_altivec()
/third_party/flutter/skia/third_party/externals/libjpeg-turbo/simd/powerpc/
Djccolext-altivec.c48 __vector int y0, y1, y2, y3, cr0, cr1, cr2, cr3, cb0, cb1, cb2, cb3; in jsimd_rgb_ycc_convert_altivec() local
249 cr0 = vec_msums(bg0, pw_mf008_mf041, pd_onehalfm1_cj); in jsimd_rgb_ycc_convert_altivec()
253 cr0 = (__vector int)vec_msum((__vector unsigned short)rg0, pw_f050_f000, in jsimd_rgb_ycc_convert_altivec()
254 (__vector unsigned int)cr0); in jsimd_rgb_ycc_convert_altivec()
261 crl = vec_perm((__vector unsigned short)cr0, in jsimd_rgb_ycc_convert_altivec()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DREADME.txt44 cmplwi cr0, r7, 143
45 bne cr0, LBB1_83 ;bb420.i
224 cmpwi cr0, r2, -1
225 bgt cr0, LBB2_2 ; entry
259 cmpwi cr0, r3, 0
261 blt cr0, LBB1_2
401 cmplwi cr0, r3, 0
404 beq cr0, LBB1_2 ;entry
464 cmplwi cr0, r6, 33920
465 bne cr0, LBB1_1
[all …]
DREADME_ALTIVEC.txt162 cmpwi cr0, r3, 0
163 bne cr0, LBB1_2 ; entry
DPPCRegisterInfo.td207 def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
DPPCInstrInfo.td3644 // cmpw cr0, r3, r2
3645 // beq cr0,L6
3648 // cmplwi cr0,r0,0x5678
3649 // beq cr0,L6
3684 // cmpd cr0, r3, r2
3685 // beq cr0,L6
3688 // cmpldi cr0,r0,0x5678
3689 // beq cr0,L6
/third_party/libffi/src/arm/
Dsysv.S135 ldcle p11, cr0, [r0] @ vldrle d0, [sp]
136 ldcgt p11, cr0, [r0], {16} @ vldmgt sp, {d0-d7}
/third_party/mesa3d/docs/relnotes/
D18.1.1.rst92 - intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0
D18.0.5.rst89 - intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0
D20.2.0.rst3425 - intel/tools: Add assembler tests for the cr0 register
3427 - intel/compiler: Don't emit no-op cr0 changes
/third_party/elfutils/tests/
Dtestfile44.expect.bz21testfile44.o: elf32-elf_i386 2 3Disassembly of section .text: 4 5 0 ...
Dtestfile45.expect.bz2
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86RegisterInfo.td342 def CR0 : X86Reg<"cr0", 0>;
/third_party/mesa3d/src/mesa/x86/
Dassyntax.h124 #define CR0 cr0
186 #define CR0 %cr0
/third_party/libbpf/.github/actions/build-selftests/
Dvmlinux.h23655 u64 cr0; member
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenAsmMatcher.inc190 return 71; // "cr0"