| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
712 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
717 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
719 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 78 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
213 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
220 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
225 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
241 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
243 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
246 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
261 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIX16Operands()
276 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeSPE8Operands()
291 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeSPE4Operands()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 88 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
319 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
329 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr20Operand()
331 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr20Operand()
341 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len4Operand()
353 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len8Operand()
365 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDRAddr12Operand()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 170 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
192 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
210 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
211 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
220 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
228 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRRX()
229 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
230 TmpInst.addOperand(MCOperand::createReg(Reg2)); in emitRRRX()
248 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRIII()
[all …]
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| D | MipsNaClELFStreamer.cpp | 105 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
106 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
107 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 1762 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
1830 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateSrcIndex()
1834 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateSrcIndex()
1855 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateDstIndex()
1941 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
1944 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
1947 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); in translateImmediate()
1961 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateImmediate()
1994 mcInst.addOperand(MCOperand::createReg(X86::x)); break; in translateRMRegister()
2039 baseReg = MCOperand::createReg(X86::x); break; in translateRMMemory()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.cpp | 40 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
43 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoop()
46 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
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| D | Thumb1InstrInfo.cpp | 28 NopInst.addOperand(MCOperand::createReg(ARM::R8)); in getNoop()
29 NopInst.addOperand(MCOperand::createReg(ARM::R8)); in getNoop()
31 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
|
| D | ARMAsmPrinter.cpp | 1402 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
1423 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1425 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1434 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
1435 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg())); in EmitInstruction()
1455 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1457 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1760 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in EmitInstruction()
1761 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
1764 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 23 TmpInst.addOperand(MCOperand::createReg(0));
84 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
90 TmpInst.addOperand(MCOperand::createReg(0));
92 TmpInst.addOperand(MCOperand::createReg(0));
189 TmpInst.addOperand(MCOperand::createReg(0));
208 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
214 TmpInst.addOperand(MCOperand::createReg(0));
216 TmpInst.addOperand(MCOperand::createReg(0));
291 TmpInst.addOperand(MCOperand::createReg(0));
306 TmpInst.addOperand(MCOperand::createReg(0));
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 2346 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
2353 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredNOperands()
2370 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredROperands()
2405 Inst.addOperand(MCOperand::createReg(getReg())); in addCCOutOperands()
2410 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
2417 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); in addRegShiftedRegOperands()
2418 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
2427 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); in addRegShiftedImmOperands()
2445 Inst.addOperand(MCOperand::createReg(*I)); in addRegListOperands()
2453 Inst.addOperand(MCOperand::createReg(*I)); in addRegListWithAPSROperands()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 953 MOVI.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
962 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
963 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
967 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
968 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
972 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
973 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); in EmitFMov0()
1037 MovZ.addOperand(MCOperand::createReg(DestReg)); in EmitInstruction()
1044 MovK.addOperand(MCOperand::createReg(DestReg)); in EmitInstruction()
1045 MovK.addOperand(MCOperand::createReg(DestReg)); in EmitInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 496 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
504 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
538 Inst.addOperand(MCOperand::createReg(Reg)); in addMaskPairOperands()
543 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addMemOperands()
545 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); in addMemOperands()
547 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands()
561 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addSrcIdxOperands()
562 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addSrcIdxOperands()
567 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addDstIdxOperands()
577 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOffsOperands()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 170 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
179 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
191 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
203 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 152 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeIntRegsRegisterClass()
163 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI64RegsRegisterClass()
175 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPRegsRegisterClass()
187 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeDFPRegsRegisterClass()
202 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeQFPRegsRegisterClass()
213 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeCPRegsRegisterClass()
222 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); in DecodeFCCRegsRegisterClass()
231 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); in DecodeASRRegsRegisterClass()
240 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); in DecodePRRegsRegisterClass()
255 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeIntPairRegisterClass()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/Disassembler/ |
| D | BPFDisassembler.cpp | 107 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
122 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
129 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeMemoryOpValue()
210 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Disassembler/ |
| D | RISCVDisassembler.cpp | 72 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
83 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
94 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass()
105 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass()
116 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass()
147 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRCRegisterClass()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 67 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
69 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
81 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
93 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
200 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
202 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
246 TmpInst.addOperand(MCOperand::createReg(Mips::RA));
258 TmpInst.addOperand(MCOperand::createReg(Mips::RA_64));
270 TmpInst.addOperand(MCOperand::createReg(Mips::RA));
282 TmpInst.addOperand(MCOperand::createReg(Mips::RA));
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 321 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR128RegisterClass()
350 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR64RegisterClass()
371 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR32RegisterClass()
392 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR16RegisterClass()
413 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR8RegisterClass()
434 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64commonRegisterClass()
445 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64RegisterClass()
457 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64spRegisterClass()
478 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32RegisterClass()
491 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32spRegisterClass()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 738 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
743 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
837 MI.insert(CCI, MCOperand::createReg(0)); in AddThumbPredicate()
839 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
854 MI.insert(VCCI, MCOperand::createReg(0)); in AddThumbPredicate()
856 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); in AddThumbPredicate()
1133 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRRegisterClass()
1147 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCLRMGPRRegisterClass()
1171 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
1186 Inst.addOperand(MCOperand::createReg(ARM::ZR)); in DecodeGPRwithZRRegisterClass()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 415 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
420 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
425 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
430 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
449 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
454 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
459 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); in addRegVFRCOperands()
464 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
469 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
474 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/MCTargetDesc/ |
| D | RISCVAsmBackend.cpp | 90 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
97 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
103 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
109 Res.addOperand(MCOperand::createReg(RISCV::X1)); in relaxInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 169 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { in createReg() function in __anon0de7a2a70111::SystemZOperand
297 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
306 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDAddrOperands()
312 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDXAddrOperands()
314 Inst.addOperand(MCOperand::createReg(Mem.Index)); in addBDXAddrOperands()
319 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDLAddrOperands()
326 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDRAddrOperands()
328 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg)); in addBDRAddrOperands()
333 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDVAddrOperands()
335 Inst.addOperand(MCOperand::createReg(Mem.Index)); in addBDVAddrOperands()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/AsmParser/ |
| D | BPFAsmParser.cpp | 188 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
204 static std::unique_ptr<BPFOperand> createReg(unsigned RegNo, SMLoc S, in createReg() function
420 Operands.push_back(BPFOperand::createReg(RegNo, S, E)); in parseRegister()
459 Operands.push_back(BPFOperand::createReg(RegNo, NameLoc, E)); in ParseInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 285 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
466 TmpInst.addOperand(MCOperand::createReg(High)); in HexagonProcessInstruction()
467 TmpInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
544 MappedInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
556 MappedInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
570 MappedInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
|