Searched refs:db_htile_surface (Results 1 – 8 of 8) sorted by relevance
2711 surf->db_htile_surface = 0; in si_init_depth_surface()2751 surf->db_htile_surface = in si_init_depth_surface()2754 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface()2823 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface()3467 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local3554 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state()3587 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
489 unsigned db_htile_surface; member
277 unsigned db_htile_surface; member
1078 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) | in r600_init_depth_surface()1554 if (a->rsurf && a->rsurf->db_htile_surface) { in r600_emit_db_state()1559 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); in r600_emit_db_state()1604 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) { in r600_emit_db_misc_state()
1433 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) | in evergreen_init_depth_surface()2050 if (a->rsurf && a->rsurf->db_htile_surface) { in evergreen_emit_db_state()2055 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); in evergreen_emit_db_state()
6540 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1) | in radv_initialise_vrs_surface()6590 ds->db_htile_surface = 0; in radv_initialise_ds_surface()6646 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1); in radv_initialise_ds_surface()6649 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in radv_initialise_ds_surface()6653 ds->db_htile_surface |= S_028ABC_VRS_HTILE_ENCODING(V_028ABC_VRS_HTILE_4BIT_ENCODING); in radv_initialise_ds_surface()6716 ds->db_htile_surface = S_028ABC_FULL_CACHE(1); in radv_initialise_ds_surface()6721 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in radv_initialise_ds_surface()
1366 uint32_t db_htile_surface; member
2160 uint32_t db_htile_surface = ds->db_htile_surface; in radv_emit_fb_ds_state() local2172 db_htile_surface &= C_028ABC_VRS_HTILE_ENCODING; in radv_emit_fb_ds_state()2176 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in radv_emit_fb_ds_state()