Searched refs:dcc_block_width (Results 1 – 6 of 6) sorted by relevance
| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_meta_dcc_retile.c | 61 nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width, surf->u.gfx9.color.dcc_block_height)); in build_dcc_retile_compute_shader()
262 unsigned dcc_width = DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width); in radv_retile_dcc()
|
| D | radv_meta_clear.c | 1436 DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width); in radv_clear_dcc_comp_to_single()
1441 image->planes[0].surface.u.gfx9.color.dcc_block_width, in radv_clear_dcc_comp_to_single()
|
| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shaderlib_nir.c | 166 coord = nir_imul(&b, coord, nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width, in si_create_dcc_retile_cs()
212 nir_channels(&b, nir_imm_ivec4(&b, tex->surface.u.gfx9.color.dcc_block_width, in gfx9_create_clear_dcc_msaa_cs()
|
| D | si_compute_blit.c | 804 unsigned width = DIV_ROUND_UP(tex->buffer.b.b.width0, tex->surface.u.gfx9.color.dcc_block_width); in si_retile_dcc()
856 unsigned width = DIV_ROUND_UP(tex->buffer.b.b.width0, tex->surface.u.gfx9.color.dcc_block_width); in gfx9_clear_dcc_msaa()
|
| /third_party/mesa3d/src/amd/common/ |
| D | ac_surface.h | 267 uint8_t dcc_block_width; member
|
| D | ac_surface.c | 1928 surf->u.gfx9.color.dcc_block_width = dout.compressBlkWidth; in gfx9_compute_miptree()
|