| /third_party/flutter/skia/third_party/externals/sdl/src/video/directfb/ |
| D | SDL_DirectFB_modes.c | 156 DFBDisplayLayerConfig dlc; in DirectFB_InitModes() local
206 dlc.flags = DLCONF_PIXELFORMAT | DLCONF_OPTIONS; in DirectFB_InitModes()
207 dlc.pixelformat = DSPF_ARGB; in DirectFB_InitModes()
208 dlc.options = DLOP_ALPHACHANNEL; in DirectFB_InitModes()
210 ret = layer->SetConfiguration(layer, &dlc); in DirectFB_InitModes()
213 dlc.pixelformat = DSPF_AiRGB; in DirectFB_InitModes()
214 SDL_DFB_CHECKERR(layer->SetConfiguration(layer, &dlc)); in DirectFB_InitModes()
219 dlc.flags = DLCONF_ALL; in DirectFB_InitModes()
220 SDL_DFB_CHECKERR(layer->GetConfiguration(layer, &dlc)); in DirectFB_InitModes()
222 mode.format = DirectFB_DFBToSDLPixelFormat(dlc.pixelformat); in DirectFB_InitModes()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SMInstructions.td | 114 (ins baseClass:$sbase, i32imm:$offset, i1imm:$glc, i1imm:$dlc),
115 " $sdst, $sbase, $offset$glc$dlc", []> {
125 (ins baseClass:$sbase, SReg_32:$soff, i1imm:$glc, i1imm:$dlc),
126 " $sdst, $sbase, $offset$glc$dlc", []> {
138 (ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, i1imm:$glc, i1imm:$dlc),
139 " $sdata, $sbase, $offset$glc$dlc", []> {
147 (ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, i1imm:$glc, i1imm:$dlc),
148 " $sdata, $sbase, $offset$glc$dlc", []> {
231 (ins dataClass:$sdata, baseClass:$sbase, smrd_offset_20:$offset, DLC:$dlc),
232 (ins dataClass:$sdata, baseClass:$sbase, SReg_32:$offset, DLC:$dlc)),
[all …]
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| D | MIMGInstructions.td | 240 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
243 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
253 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
256 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
333 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc,
336 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
347 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
350 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
438 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc,
440 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe";
[all …]
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| D | BUFInstructions.td | 101 bits<1> dlc_value = 0; // the value for dlc if no such operand
125 bits<1> dlc;
144 offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz),
146 offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz)
151 SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz),
154 SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz)
206 " $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe$dlc$swz",
222 i1:$glc, i1:$slc, i1:$tfe, i1:$dlc, i1:$swz)))]>,
228 i8:$format, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc, i1:$swz)))]>,
254 " $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe$dlc$swz",
[all …]
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| D | FLATInstructions.td | 93 bits<1> dlc;
145 (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
147 " $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
166 (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
167 …" $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
200 (ins SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
201 (ins VGPR_32:$vaddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
202 … "#!if(EnableSaddr, "off", "$vaddr")#!if(EnableSaddr, ", $saddr", ", off")#"$offset$glc$slc$dlc"> {
216 …ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
217 (ins vdataClass:$vdata, VGPR_32:$vaddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
[all …]
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| D | SIFixupVectorISel.cpp | 200 MachineOperand *DLC = TII->getNamedOperand(MI, AMDGPU::OpName::dlc); in fixupGlobalSaddr()
|
| D | SIInstrFormats.td | 305 bits<1> dlc;
311 let Inst{7} = dlc;
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| D | SIMemoryLegalizer.cpp | 362 return enableNamedBit<AMDGPU::OpName::dlc>(MI); in enableDLCBit()
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| D | SILoadStoreOptimizer.cpp | 515 DLC = TII.getNamedOperand(*I, AMDGPU::OpName::dlc)->getImm(); in setMI()
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| D | SIInstrInfo.cpp | 4780 getNamedOperand(MI, AMDGPU::OpName::dlc)) { in legalizeOperands()
|
| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_opt_value_numbering.cpp | 216 return aS.sync == bS.sync && aS.glc == bS.glc && aS.dlc == bS.dlc && aS.nv == bS.nv && in operator ()()
257 aM.glc == bM.glc && aM.dlc == bM.dlc && aM.slc == bM.slc && aM.tfe == bM.tfe && in operator ()()
264 aM.idxen == bM.idxen && aM.glc == bM.glc && aM.dlc == bM.dlc && aM.slc == bM.slc && in operator ()()
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| D | aco_assembler.cpp | 209 assert(!smem.dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
214 encoding |= smem.dlc ? 1 << 14 : 0; in emit_instruction()
390 assert(!mubuf.dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
393 encoding |= (mubuf.dlc ? 1 : 0) << 15; in emit_instruction()
417 assert(!mtbuf.dlc || ctx.gfx_level >= GFX10); in emit_instruction()
418 encoding |= (mtbuf.dlc ? 1 : 0) << 15; /* DLC bit replaces one bit of the OPCODE on GFX10 */ in emit_instruction()
464 assert(!mimg.dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
473 encoding |= mimg.dlc ? 1 << 7 : 0; in emit_instruction()
534 encoding |= flat.dlc ? 1 << 12 : 0; in emit_instruction()
536 assert(!flat.dlc); in emit_instruction()
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| D | aco_print_ir.cpp | 343 if (smem.dlc) in print_instr_format_specific()
378 if (mubuf.dlc) in print_instr_format_specific()
413 if (mimg.dlc) in print_instr_format_specific()
490 if (flat.dlc) in print_instr_format_specific()
542 if (mtbuf.dlc) in print_instr_format_specific()
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| D | aco_ir.h | 1397 bool dlc : 1; /* NAVI: device level coherent */ member
1567 bool dlc : 1; /* NAVI: device level coherent */ member
1595 uint16_t dlc : 1; /* NAVI: device level coherent */ member
1619 bool dlc : 1; /* NAVI: device level coherent */ member
1646 bool dlc : 1; /* NAVI: device level coherent */ member
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| D | aco_instruction_selection.cpp | 4394 load->dlc = info.glc && (bld.program->gfx_level == GFX10 || bld.program->gfx_level == GFX10_3); in smem_load_callback()
4442 mubuf->dlc = in mubuf_load_callback()
4655 mubuf->dlc = false; in global_load_callback()
4675 flat->dlc = in global_load_callback()
6280 load->dlc = in visit_image_load()
6297 load->dlc = in visit_image_load()
6371 store->dlc = false; in visit_image_store()
6424 store->dlc = false; in visit_image_store()
6541 mubuf->dlc = false; /* Not needed for atomics */ in visit_image_atomic()
6558 mimg->dlc = false; /* Not needed for atomics */ in visit_image_atomic()
[all …]
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| D | aco_optimizer.cpp | 881 new_instr->dlc = smem.dlc; in smem_combine()
|
| /third_party/gstreamer/gstplugins_bad/ext/directfb/ |
| D | dfbvideosink.c | 653 DFBDisplayLayerConfig dlc; in gst_dfbvideosink_enum_layers() local
684 ret = layer->GetConfiguration (layer, &dlc); in gst_dfbvideosink_enum_layers()
691 if ((dlc.flags & DLCONF_BUFFERMODE) && (dlc.buffermode & DLBM_FRONTONLY)) { in gst_dfbvideosink_enum_layers()
694 if ((dlc.flags & DLCONF_BUFFERMODE) && (dlc.buffermode & DLBM_BACKVIDEO)) { in gst_dfbvideosink_enum_layers()
698 if ((dlc.flags & DLCONF_BUFFERMODE) && (dlc.buffermode & DLBM_BACKSYSTEM)) { in gst_dfbvideosink_enum_layers()
702 if ((dlc.flags & DLCONF_BUFFERMODE) && (dlc.buffermode & DLBM_TRIPLE)) { in gst_dfbvideosink_enum_layers()
1213 DFBDisplayLayerConfig dlc, prev_dlc; in gst_dfbvideosink_can_blit_from_format() local
1239 dlc.flags = DLCONF_PIXELFORMAT; in gst_dfbvideosink_can_blit_from_format()
1240 dlc.pixelformat = format; in gst_dfbvideosink_can_blit_from_format()
1242 ret = dfbvideosink->layer->TestConfiguration (dfbvideosink->layer, &dlc, in gst_dfbvideosink_can_blit_from_format()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 699 …lvm_i32_ty]), // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc)
873 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 2 = dlc)
904 // bit 2 = dlc on gfx10+),
919 // bit 2 = dlc on gfx10+),
934 // bit 2 = dlc on gfx10+),
950 // bit 2 = dlc on gfx10+),
1067 // bit 2 = dlc on gfx10+),
1081 // bit 2 = dlc on gfx10+),
1095 // bit 2 = dlc on gfx10+),
1110 // bit 2 = dlc on gfx10+),
|
| /third_party/node/deps/icu-small/source/i18n/ |
| D | rbnf.cpp | 148 int32_t dlc = getNumberOfDisplayLocales(); in operator ==() local
149 if (dlc == rhs->getNumberOfDisplayLocales()) { in operator ==()
150 for (int i = 0; i < dlc; ++i) { in operator ==()
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| /third_party/skia/third_party/externals/icu/source/i18n/ |
| D | rbnf.cpp | 148 int32_t dlc = getNumberOfDisplayLocales(); in operator ==() local
149 if (dlc == rhs->getNumberOfDisplayLocales()) { in operator ==()
150 for (int i = 0; i < dlc; ++i) { in operator ==()
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| /third_party/flutter/skia/third_party/externals/icu/source/i18n/ |
| D | rbnf.cpp | 148 int32_t dlc = getNumberOfDisplayLocales(); in operator ==() local
149 if (dlc == rhs->getNumberOfDisplayLocales()) { in operator ==()
150 for (int i = 0; i < dlc; ++i) { in operator ==()
|
| /third_party/icu/icu4c/source/i18n/ |
| D | rbnf.cpp | 148 int32_t dlc = getNumberOfDisplayLocales(); in operator ==() local
149 if (dlc == rhs->getNumberOfDisplayLocales()) { in operator ==()
150 for (int i = 0; i < dlc; ++i) { in operator ==()
|
| /third_party/mesa3d/docs/relnotes/ |
| D | 20.0.0.rst | 2790 - aco: set dlc/glc correctly for image loads
|
| /third_party/chromium/patch/ |
| D | 0001-cve.patch | 61950 zteRDAs-{#Es-fIKZb0SxP=_;yRg0>ARd23e)dlc|=mAx?YEtD?*>b0Ir&UIkj-f;R
|