| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_optimizer_postRA.cpp | 423 bool dpp8 = mov->isDPP8(); in try_combine_dpp() local
424 if (!can_use_DPP(instr, false, dpp8)) in try_combine_dpp()
441 if (!dpp8) /* anything else doesn't make sense in SSA */ in try_combine_dpp()
447 convert_to_DPP(instr, dpp8); in try_combine_dpp()
449 if (dpp8) { in try_combine_dpp()
450 DPP8_instruction* dpp = &instr->dpp8(); in try_combine_dpp()
455 memcpy(dpp->lane_sel, mov->dpp8().lane_sel, sizeof(dpp->lane_sel)); in try_combine_dpp()
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| D | aco_ir.cpp | 315 can_use_DPP(const aco_ptr<Instruction>& instr, bool pre_ra, bool dpp8) in can_use_DPP() argument
320 return instr->isDPP8() == dpp8; in can_use_DPP()
339 if (dpp8) in can_use_DPP()
356 convert_to_DPP(aco_ptr<Instruction>& instr, bool dpp8) in convert_to_DPP() argument
363 (dpp8 ? (uint32_t)Format::DPP8 : (uint32_t)Format::DPP16)); in convert_to_DPP()
364 if (dpp8) in convert_to_DPP()
374 if (dpp8) { in convert_to_DPP()
375 DPP8_instruction* dpp = &instr->dpp8(); in convert_to_DPP()
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| D | aco_opt_value_numbering.cpp | 188 DPP8_instruction& aDPP = a->dpp8(); in operator ()()
189 DPP8_instruction& bDPP = b->dpp8(); in operator ()()
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| D | aco_ir.h | 1314 DPP8_instruction& dpp8() noexcept in dpp8() function
1319 const DPP8_instruction& dpp8() const noexcept in dpp8() function
1802 bool can_use_DPP(const aco_ptr<Instruction>& instr, bool pre_ra, bool dpp8);
1805 aco_ptr<Instruction> convert_to_DPP(aco_ptr<Instruction>& instr, bool dpp8);
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| D | aco_optimizer.cpp | 2452 DPP8_instruction& cmp_dpp = cmp->dpp8(); in combine_inverse_comparison()
4503 bool dpp8 = info.is_dpp8(); in select_instruction() local
4504 convert_to_DPP(instr, dpp8); in select_instruction()
4505 if (dpp8) { in select_instruction()
4506 DPP8_instruction* dpp = &instr->dpp8(); in select_instruction()
4508 dpp->lane_sel[j] = info.instr->dpp8().lane_sel[j]; in select_instruction()
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| D | aco_print_ir.cpp | 610 const DPP8_instruction& dpp = instr->dpp8(); in print_instr_format_specific()
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| D | aco_assembler.cpp | 698 DPP8_instruction& dpp = instr->dpp8(); in emit_instruction()
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| D | aco_instruction_selection.cpp | 259 ret.instr->dpp8().lane_sel[i] = (((i & and_mask) | or_mask) ^ xor_mask) & 0x7; in emit_masked_swizzle()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.td | 1080 def dpp8 : NamedOperandU32<"DPP8", NamedMatchClass<"DPP8", 0>>;
1792 (ins dpp8:$dpp8, FI:$fi),
1797 Src0RC:$src0, dpp8:$dpp8, FI:$fi)
1800 (ins DstRC:$old, Src0RC:$src0, dpp8:$dpp8, FI:$fi)
1808 dpp8:$dpp8, FI:$fi)
1812 Src0RC:$src0, Src1RC:$src1, dpp8:$dpp8, FI:$fi)
1990 string ret = dst#args#"$dpp8$fi";
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| D | VOP1Instructions.td | 295 let InsDPP8 = (ins Src0RC32:$old, Src0RC32:$src0, dpp8:$dpp8, FI:$fi);
909 (i32 (int_amdgcn_mov_dpp8 i32:$src, timm:$dpp8)),
910 (V_MOV_B32_dpp8_gfx10 $src, $src, (as_i32imm $dpp8), (i32 DPP8Mode.FI_0))
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| D | VOP2Instructions.td | 300 dpp8:$dpp8, FI:$fi);
349 let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi";
363 let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi";
398 let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";
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| D | VOPInstructions.td | 683 bits<24> dpp8;
687 let Inst{63-40} = dpp8{23-0};
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| D | AMDGPU.td | 354 def FeatureDPP8 : SubtargetFeature<"dpp8",
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 1581 // llvm.amdgcn.mov.dpp8.i32 <src> <sel>
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicImpl.inc | 1430 "llvm.amdgcn.mov.dpp8",
11563 76, // llvm.amdgcn.mov.dpp8
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