Home
last modified time | relevance | path

Searched refs:dsub (Results 1 – 17 of 17) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp119 SubReg == AArch64::dsub); in isFPR64()
122 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
138 SubReg = AArch64::dsub; in getSrcFromCopy()
DAArch64InstrInfo.td2104 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
2106 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
2269 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
2841 defm : VecROStoreLane0Pat<ro64, store, v2i64, i64, dsub, STRDroW, STRDroX>;
2842 defm : VecROStoreLane0Pat<ro64, store, v2f64, f64, dsub, STRDroW, STRDroX>;
2963 defm : VecStoreLane0Pat<am_indexed64, store, v2i64, i64, dsub, uimm12s8, STRDui>;
2964 defm : VecStoreLane0Pat<am_indexed64, store, v2f64, f64, dsub, uimm12s8, STRDui>;
3096 defm : VecStoreULane0Pat<store, v2i64, i64, dsub, STURDi>;
3097 defm : VecStoreULane0Pat<store, v2f64, f64, dsub, STURDi>;
3698 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
[all …]
DAArch64InstructionSelector.cpp413 SubReg = AArch64::dsub; in getSubRegForClass()
2799 return BuildFn(AArch64::dsub); in emitScalarToVector()
2890 ExtractSubReg = AArch64::dsub; in getLaneCopyOpcode()
3099 .addImm(AArch64::dsub); in selectUnmergeValues()
3216 SubregIdx = AArch64::dsub; in getInsertVecEltOpInfo()
3232 SubregIdx = AArch64::dsub; in getInsertVecEltOpInfo()
3840 .addReg(TBL1.getReg(0), 0, AArch64::dsub); in selectShuffleVector()
3953 if (SubReg != AArch64::ssub && SubReg != AArch64::dsub) { in selectInsertElt()
4021 if (SubReg != AArch64::ssub && SubReg != AArch64::dsub) { in selectBuildVector()
DAArch64RegisterInfo.td27 def dsub : SubRegIndex<32>;
387 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
DAArch64InstrInfo.cpp2701 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub, in copyPhysReg()
2703 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub, in copyPhysReg()
3354 case AArch64::dsub: in foldMemoryOperandImpl()
3357 SpillSubreg = AArch64::dsub; in foldMemoryOperandImpl()
3393 case AArch64::dsub: in foldMemoryOperandImpl()
DAArch64InstrFormats.td5853 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
5856 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
5859 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
6036 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
6132 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
6137 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
6142 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7848 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
7858 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
8792 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
[all …]
DAArch64ISelDAGToDAG.cpp1396 return DAG.getTargetInsertSubreg(AArch64::dsub, DL, WideTy, Undef, V64Reg); in operator ()()
1409 return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy, in NarrowVector()
DAArch64ISelLowering.cpp5123 setVecVal(AArch64::dsub); in LowerFCOPYSIGN()
5150 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel); in LowerFCOPYSIGN()
6533 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg); in NarrowVector()
DSVEInstrFormats.td6515 …def : SVE_2_Op_Pat_Reduce_To_Neon<v2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D), dsub>;
6527 …def : SVE_2_Op_Pat_Reduce_To_Neon<v2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D), dsub>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterInfo.inc788 dsub, // 2
1117 { 0, 32 }, // dsub
5191 static const char *const SubRegIndexNameTable[] = { "bsub", "dsub", "dsub0", "dsub1", "dsub2", "dsu…
5197 LaneBitmask(0x00000001), // dsub
5535 0x00000000, 0xffffe7c0, 0xffffffff, 0x00000fff, // dsub
8940 …{ AArch64::bsub, AArch64::dsub, AArch64::dsub0, AArch64::dsub1, AArch64::dsub2, 0, AArch64::hsub, …
8950 …{ AArch64::bsub, AArch64::dsub, AArch64::dsub, AArch64::qsub1_then_dsub, AArch64::qsub2_then_dsub,…
8951 …{ AArch64::bsub, 0, AArch64::dsub, AArch64::zsub1_then_dsub, AArch64::zsub2_then_dsub, AArch64::zs…
9018 &LaneMaskComposeSequences[0], // to dsub
9149 0, // dsub
[all …]
DAArch64GenGlobalISel.inc6998 …(INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] })
7019 …(INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] })
7038 …*:[v1i64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[…
7078 …*:[v1f64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[…
7141 …T_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:…
7181 …T_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:…
7221 …T_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:…
7261 …T_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:…
7301 …T_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:…
7341 …T_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:…
[all …]
/third_party/ltp/tools/sparse/sparse-src/validation/backend/
Darithmetic-ops.c36 static double dsub(double x, double y) in dsub() function
/third_party/python/Tools/scripts/
Ddutree.py42 tsub, dsub = d[key]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips64InstrInfo.td149 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
999 def : MipsInstAlias<"dsub $rs, $rt, $imm",
1003 def : MipsInstAlias<"dsub $rs, $imm",
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64InstPrinter.cpp1294 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); in printVectorList()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc6508 …{ 3920 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasS…
6509 …{ 3920 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEn…
6510 …{ 3920 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasS…
6511 …{ 3920 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEn…
9756 { 3920 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9757 { 3920 /* dsub */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9758 { 3920 /* dsub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9759 { 3920 /* dsub */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9760 …{ 3920 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6…
9761 { 3920 /* dsub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
/third_party/libffi/
DChangeLog.old2794 * src/mips/n32.S (ffi_call_N32): Replace dadd with ADDU, dsub with