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Searched refs:ge_cntl (Results 1 – 4 of 4) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_draw.cpp1314 unsigned ge_cntl; in gfx10_emit_ge_cntl() local
1320 … G_03096C_PRIM_GRP_SIZE_GFX11(si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ge_cntl); in gfx10_emit_ge_cntl()
1322 ge_cntl = S_03096C_PRIMS_PER_SUBGRP(num_patches) | in gfx10_emit_ge_cntl()
1327 ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(num_patches) | in gfx10_emit_ge_cntl()
1332 ge_cntl = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ge_cntl; in gfx10_emit_ge_cntl()
1351 ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(primgroup_size) | in gfx10_emit_ge_cntl()
1356 ge_cntl |= S_03096C_PACKET_TO_ONE_PA(si_is_line_stipple_enabled(sctx)); in gfx10_emit_ge_cntl()
1358 if (ge_cntl != sctx->last_multi_vgt_param) { in gfx10_emit_ge_cntl()
1362 radeon_set_uconfig_reg(R_03096C_GE_CNTL, ge_cntl); in gfx10_emit_ge_cntl()
1364 sctx->last_multi_vgt_param = ge_cntl; in gfx10_emit_ge_cntl()
Dsi_shader.h956 unsigned ge_cntl; member
Dsi_state_shaders.cpp1516 shader->ge_cntl = S_03096C_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) | in gfx10_shader_ngg()
1521 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(shader->ngg.max_gsprims) | in gfx10_shader_ngg()
1546 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE; in gfx10_shader_ngg()
1547 shader->ge_cntl |= S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5); in gfx10_shader_ngg()
/third_party/mesa3d/src/amd/vulkan/
Dradv_pipeline.c5787 unsigned ge_cntl; in radv_pipeline_emit_hw_ngg() local
5864 ge_cntl = S_03096C_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) | in radv_pipeline_emit_hw_ngg()
5871 ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(ngg_state->max_gsprims) | in radv_pipeline_emit_hw_ngg()
5885 ge_cntl &= C_03096C_VERT_GRP_SIZE; in radv_pipeline_emit_hw_ngg()
5888 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5); in radv_pipeline_emit_hw_ngg()
5892 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl); in radv_pipeline_emit_hw_ngg()