| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyCallIndirectFixup.cpp | 130 make_range(MI.operands_begin() + MI.getDesc().getNumDefs() + 1, in runOnMachineFunction()
133 Ops.push_back(MI.getOperand(MI.getDesc().getNumDefs())); in runOnMachineFunction()
136 while (MI.getNumOperands() > MI.getDesc().getNumDefs()) in runOnMachineFunction()
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| D | WebAssemblyExplicitLocals.cpp | 274 assert(MI.getDesc().getNumDefs() <= 1); in runOnMachineFunction()
275 if (MI.getDesc().getNumDefs() == 1) { in runOnMachineFunction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 92 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
128 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) { in init()
182 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
496 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly()
513 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(), in registerUsed()
531 for (unsigned J = 0, N = Desc.getNumDefs(); J < N; ++J) in registerProducer()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 2055 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
2057 if (II.getNumDefs() >= 1) in fastEmitInst_r()
2077 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2078 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
2080 if (II.getNumDefs() >= 1) in fastEmitInst_rr()
2102 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
2103 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
2104 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2106 if (II.getNumDefs() >= 1) in fastEmitInst_rrr()
2128 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
[all …]
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| D | ScheduleDAGSDNodes.cpp | 127 if (ResNo >= II.getNumDefs() && in CheckForPhysRegDependency()
128 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) in CheckForPhysRegDependency()
468 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) in AddSchedEdges()
567 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs(); in InitNodeNumDefs()
654 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); in computeOperandLatency()
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| D | ScheduleDAGRRList.cpp | 1285 NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1418 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) in DelayForLiveRegsBottomUp()
2114 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in MayReduceRegPressure()
2160 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in RegPressureDiff()
2289 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2306 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2820 unsigned NumRes = MCID.getNumDefs(); in canClobber()
2877 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in canClobberPhysRegDefs()
3065 unsigned NumRes = MCID.getNumDefs(); in AddPseudoTwoAddrDeps()
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| D | InstrEmitter.cpp | 134 if (i+II.getNumDefs() < II.getNumOperands()) { in EmitCopyFromReg()
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
198 for (unsigned i = 0; i < II.getNumDefs(); ++i) { in CreateVirtualRegisters()
813 unsigned NumDefs = II.getNumDefs(); in EmitMachineNode()
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| D | ResourcePriorityQueue.cpp | 544 NodeNumDefs = std::min(N->getNumValues(), TID.getNumDefs()); in initNumRegDefsLeft()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ExecutionDomainFix.cpp | 239 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
259 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
290 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
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| D | PeepholeOptimizer.cpp | 870 NumDefs = MI.getDesc().getNumDefs(); in UncoalescableRewriter()
1170 assert(MI.getDesc().getNumDefs() == 1 && in optimizeCoalescableCopy()
1316 if (MCID.getNumDefs() != 1) in isLoadFoldable()
1337 if (MCID.getNumDefs() != 1) in isMoveImmediate()
1518 if (MI.getDesc().getNumDefs() != 1) in findTargetRecurrence()
1757 for (unsigned i = MIDesc.getNumDefs(); i != MI->getNumOperands(); in runOnMachineFunction()
1837 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
2053 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
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| D | DetectDeadLanes.cpp | 281 if (MI.getDesc().getNumDefs() != 1) in transferDefinedLanesStep()
429 assert(UseMI.getDesc().getNumDefs() == 1); in determineInitialUsedLanes()
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| D | BreakFalseDeps.cpp | 200 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
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| D | MachineCSE.cpp | 593 unsigned NumDefs = MI->getNumDefs(); in ProcessBlockCSE()
777 MI->getNumDefs() != 1 || in isPRECandidate()
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| D | ReachingDefAnalysis.cpp | 104 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
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| D | LiveRangeEdit.cpp | 293 MI->getDesc().getNumDefs() == 1) { in eliminateDeadDef()
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| D | ImplicitNullChecks.cpp | 622 unsigned NumDefs = MI->getDesc().getNumDefs(); in insertFaultingInstr()
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| D | TargetInstrInfo.cpp | 161 bool HasDef = MCID.getNumDefs(); in commuteInstructionImpl()
298 unsigned CommutableOpIdx1 = MCID.getNumDefs(); in findCommutedOpIndices()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/ |
| D | InstrBuilder.cpp | 221 unsigned NumExplicitDefs = MCDesc.getNumDefs(); in verifyOperands()
295 unsigned NumExplicitDefs = MCDesc.getNumDefs(); in populateWrites()
420 unsigned NumExplicitUses = MCDesc.getNumOperands() - MCDesc.getNumDefs(); in populateReads()
429 for (unsigned I = 0, OpIndex = MCDesc.getNumDefs(); I < NumExplicitUses; in populateReads()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| D | WebAssemblyInstPrinter.cpp | 216 else if (OpNo >= MII.get(MI->getOpcode()).getNumDefs()) in printOperand()
223 if (OpNo < MII.get(MI->getOpcode()).getNumDefs()) in printOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64DeadRegisterDefinitionsPass.cpp | 142 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) { in processMachineBasicBlock()
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| D | AArch64FastISel.cpp | 1141 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1143 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1344 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1345 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1389 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1431 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1432 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1476 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1477 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2171 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitStore()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Localizer.cpp | 127 assert(MI.getDesc().getNumDefs() == 1 && in localizeInterBlock()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 250 unsigned getNumDefs() const { return NumDefs; } in getNumDefs() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZHazardRecognizer.cpp | 126 if (OpIdx >= MID.getNumDefs() && in has4RegOps()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 2076 if (II.getNumDefs()) { in X86FastEmitCMoveSelect()
3984 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrrr()
3985 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrrr()
3986 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrrr()
3987 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
3989 if (II.getNumDefs() >= 1) in fastEmitInst_rrrr()
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