| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 984 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) in getOperandBias()
989 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0) in getOperandBias()
994 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
995 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) in getOperandBias()
999 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
1000 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 || in getOperandBias()
1001 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1)) in getOperandBias()
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| D | X86InstComments.cpp | 237 if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1) in printMasking()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 212 int getOperandConstraint(unsigned OpNum, in getOperandConstraint() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZHazardRecognizer.cpp | 127 MID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in has4RegOps()
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| D | SystemZShortenInst.cpp | 67 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in tieOpsIfNeeded()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 214 if (MCID.getOperandConstraint(I, MCOI::TIED_TO) != -1) in ClusterNeighboringLoads()
451 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
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| D | ScheduleDAGFast.cpp | 256 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
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| D | ScheduleDAGRRList.cpp | 1036 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in TryUnfoldSU()
2823 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) { in canClobber()
3068 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1) in AddPseudoTwoAddrDeps()
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| D | InstrEmitter.cpp | 350 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; in AddRegisterOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 150 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); in constrainSelectedInstRegOperands()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 281 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand()
286 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) in addOperand()
1415 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); in hasComplexRegisterTies()
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| D | TargetInstrInfo.cpp | 197 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
202 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
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| D | RegAllocFast.cpp | 1053 MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1; in allocateInstruction()
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| D | MachineVerifier.cpp | 1617 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); in visitMachineOperand()
1661 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO)) in visitMachineOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 402 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, in getInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2896 Desc.getOperandConstraint(DstIdx, MCOI::EARLY_CLOBBER) == -1) { in validateEarlyClobberLimitations()
6231 && Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1; in isRegOrImmWithInputMods()
6729 auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(), in cvtDPP()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 2154 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(), in findCommutedOpIndices()
4846 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; in foldMemoryOperandImpl()
4947 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO); in foldMemoryOperandImpl()
4949 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO); in foldMemoryOperandImpl()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 407 assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in commuteInstructionImpl()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3927 (MCID.getOperandConstraint(i, MCOI::TIED_TO) == -1) && in validateInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 858 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( in AddThumbPredicate()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 2365 int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO); in addVPTPredROperands()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 10901 int DefIdx = MCID->getOperandConstraint(i, MCOI::TIED_TO); in AdjustInstrPostInstrSelection()
|