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Searched refs:gpr_regs (Results 1 – 5 of 5) sorted by relevance

/third_party/mesa3d/src/freedreno/afuc/
Demu-regs.c203 uint32_t rem = emu->gpr_regs.val[REG_REM]; in emu_get_fifo_reg()
233 emu->gpr_regs.val[n] = val; in emu_set_fifo_reg()
234 BITSET_SET(emu->gpr_regs.written, n); in emu_set_fifo_reg()
246 unsigned regoff = emu->gpr_regs.val[reg]; in emu_set_fifo_reg()
260 emu->gpr_regs.val[reg] = regoff + 0x01000000; in emu_set_fifo_reg()
261 BITSET_SET(emu->gpr_regs.written, reg); in emu_set_fifo_reg()
276 assert(n < ARRAY_SIZE(emu->gpr_regs.val)); in emu_get_gpr_reg()
287 return emu->gpr_regs.val[n]; in emu_get_gpr_reg()
294 assert(n < ARRAY_SIZE(emu->gpr_regs.val)); in emu_set_gpr_reg()
303 emu->gpr_regs.val[n] = val; in emu_set_gpr_reg()
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Demu-ui.c151 if (BITSET_TEST(emu->gpr_regs.written, n)) { in dump_gpr_register()
152 printdelta("%08x\n", emu->gpr_regs.val[n]); in dump_gpr_register()
154 printf("%08x\n", emu->gpr_regs.val[n]); in dump_gpr_register()
161 for (unsigned i = 0; i < ARRAY_SIZE(emu->gpr_regs.val); i++) { in dump_gpr_registers()
502 memset(emu->gpr_regs.written, 0, sizeof(emu->gpr_regs.written)); in emu_clear_state_change()
515 BITSET_FOREACH_SET (i, emu->gpr_regs.written, EMU_NUM_GPR_REGS) { in emu_dump_state_change()
Demu.c249 uint32_t off = emu->gpr_regs.pc + instr->br.ioff; in emu_instr()
283 emu->call_stack[emu->call_stack_idx++] = emu->gpr_regs.pc + 2; in emu_instr()
314 afuc_instr *instr = (void *)&emu->instrs[emu->gpr_regs.pc]; in emu_step()
347 emu->gpr_regs.pc++; in emu_step()
350 emu->gpr_regs.pc = branch_target; in emu_step()
367 emu->gpr_regs.val[1] &= 0x0fffffff; in emu_step()
379 emu->gpr_regs.pc = emu->jmptbl[id]; in emu_step()
Demu.h167 struct emu_gpr_regs gpr_regs; member
Ddisasm.c773 disasm_instr(emu->instrs, emu->gpr_regs.pc); in disasm()
798 disasm_instr(emu->instrs, emu->gpr_regs.pc); in disasm()