Searched refs:hasSuperClassEq (Results 1 – 13 of 13) sorted by relevance
139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()517 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()518 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()534 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()540 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
111 (RC->hasSuperClassEq(&ARM::tGPRRegClass) || in loadRegFromStackSlot()115 if (RC->hasSuperClassEq(&ARM::tGPRRegClass) || in loadRegFromStackSlot()
109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
2040 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()2041 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()2043 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()2077 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()2078 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()2079 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()2081 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()2082 bool Is256Bit = OpRC->hasSuperClassEq(&X86::VR256XRegClass); in hardenLoadAddr()2110 assert(OpRC->hasSuperClassEq(&X86::GR64RegClass) && in hardenLoadAddr()2263 return RC->hasSuperClassEq(GPRRegClasses[RegIdx]); in canHardenRegister()
226 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 && in shouldRewriteCopySrc()227 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit) in shouldRewriteCopySrc()
46819 return RC.hasSuperClassEq(&X86::GR8RegClass) || in isGRClass()46820 RC.hasSuperClassEq(&X86::GR16RegClass) || in isGRClass()46821 RC.hasSuperClassEq(&X86::GR32RegClass) || in isGRClass()46822 RC.hasSuperClassEq(&X86::GR64RegClass) || in isGRClass()46823 RC.hasSuperClassEq(&X86::LOW32_ADDR_ACCESS_RBPRegClass); in isGRClass()46829 return RC.hasSuperClassEq(&X86::FR32XRegClass) || in isFRClass()46830 RC.hasSuperClassEq(&X86::FR64XRegClass) || in isFRClass()46831 RC.hasSuperClassEq(&X86::VR128XRegClass) || in isFRClass()46832 RC.hasSuperClassEq(&X86::VR256XRegClass) || in isFRClass()46833 RC.hasSuperClassEq(&X86::VR512RegClass); in isFRClass()[all …]
476 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad()496 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad()630 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitStore()1284 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in SelectBinaryIntOp()2117 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCMaterialize32BitInt()
192 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()193 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()3847 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? in transformToImmFormFedByLI()
350 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && in shouldCoalesce()
135 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() function
1802 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
83 return RC->hasSuperClassEq(TRI.getBoolRC()) && in isVCC()
3944 return RC->hasSuperClassEq(DRC); in isLegalRegOperand()