Searched refs:jalr (Results 1 – 25 of 32) sorted by relevance
12
77 jalr t9150 jalr t9158 jalr t9166 jalr t9177 jalr t9188 jalr t9361 jalr t9
513 jalr t9
63 l.jalr r575 l.jalr r16
13 jalr $25
18 jalr $25
27 l.jalr r11
32 jalr $25
30 jalr a1
30 jalr $25 # call the user's function
22 jalr $25
386 "jalr", "$rd, ${imm12}(${rs1})">,638 // Non-zero offset aliases of "jalr" are the lowest weight, followed by the642 def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0), 3>;643 def : InstAlias<"jalr ${offset}(${rs})", (JALR X1, GPR:$rs, simm12:$offset)>;644 def : InstAlias<"jalr $rd, $rs", (JALR GPR:$rd, GPR:$rs, 0), 2>;649 def : InstAlias<"jalr $rs, $offset", (JALR X1, GPR:$rs, simm12:$offset), 0>;650 def : InstAlias<"jalr $rd, $rs, $offset", (JALR GPR:$rd, GPR:$rs, simm12:$offset), 0>;915 // expand to auipc and jalr while encoding, with any given register used as the926 // and jalr while encoding. This is desirable, as an auipc+jalr pair with953 // expand to auipc and jalr while encoding.
181 jalr FNADDR
124 jalr t1
... jr zero 32 6c: 67 85 00 80 jalr a0,-2048(ra) 33 70: ...
191 void jalr(const Operand *OpRs, const Operand *OpRd);
499 Asm->jalr(getCallTarget(), ImplicitRA); in emitIAS()
34 // Reencoded: jr -> jalr35 // Reencoded: jr.hb -> jalr.hb
262 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM, PTR_64;1043 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB64 RA_64, GPR64Opnd:$rs), 1>,
678 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,973 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>,
285 // jalr, jr.hb, jr, jalr.hb, jarlc, jialc
5026 "insve.w\001j\003jal\004jalr\007jalr.hb\005jalrc\010jalrc.hb\005jalrs\007"6755 …{ 5304 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_…6756 …{ 5304 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { M…6757 …{ 5304 /* jalr */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, AMFBS_NotInMicroMips, { MCK_GPR32As…6758 …{ 5304 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicro…6759 …{ 5304 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMi…6760 …{ 5304 /* jalr */, Mips::JALR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_NotInMips16Mode_Is…6761 …{ 5309 /* jalr.hb */, Mips::JALR_HB, Convert__regRA__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32_Not…6762 …{ 5309 /* jalr.hb */, Mips::JALR_HB64, Convert__regRA_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips6…6763 …{ 5309 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasM…[all …]