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Searched refs:ldc1 (Results 1 – 9 of 9) sorted by relevance

/third_party/musl/src/setjmp/mipsn32/
Dlongjmp.S14 ldc1 $24, 96($4)
15 ldc1 $25, 104($4)
16 ldc1 $26, 112($4)
17 ldc1 $27, 120($4)
18 ldc1 $28, 128($4)
19 ldc1 $29, 136($4)
20 ldc1 $30, 144($4)
21 ldc1 $31, 152($4)
/third_party/musl/src/setjmp/mips64/
Dlongjmp.S15 ldc1 $24, 96($4)
16 ldc1 $25, 104($4)
17 ldc1 $26, 112($4)
18 ldc1 $27, 120($4)
19 ldc1 $28, 128($4)
20 ldc1 $29, 136($4)
21 ldc1 $30, 144($4)
22 ldc1 $31, 152($4)
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.h195 void ldc1(const Operand *OpRt, const Operand *OpBase, const Operand *OpOff,
DIceInstMIPS32.cpp814 Asm->ldc1(getDest(), Mem->getBase(), Mem->getOffset(), Reloc); in emitIAS()
DIceAssemblerMIPS32.cpp684 void AssemblerMIPS32::ldc1(const Operand *OpRt, const Operand *OpBase, in ldc1() function in Ice::MIPS32::AssemblerMIPS32
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstrFPU.td573 def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>,
582 def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1,
DMicroMipsInstrFPU.td281 def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
DMicroMips32r6InstrInfo.td228 class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>;
761 string AsmString = !strconcat("ldc1", "\t$ft, $addr");
765 string BaseOpcode = "ldc1";
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc5030 "ldc1\004ldc2\004ldc3\005ldi.b\005ldi.d\005ldi.h\005ldi.w\003ldl\004ldpc"
6828 …{ 5477 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_Not…
6829 …{ 5477 /* ldc1 */, Mips::LDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMip…
6830 …{ 5477 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_Is…
6831 …{ 5477 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMic…
10116 …{ 5477 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat…
10117 …{ 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoft…
10118 { 5477 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
10119 …{ 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
10120 …{ 5477 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_N…
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