| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_sqtt.c | 84 unsigned max_se = rad_info->max_se; in radv_emit_thread_trace_start() local
86 for (unsigned se = 0; se < max_se; se++) { in radv_emit_thread_trace_start()
259 unsigned max_se = device->physical_device->rad_info.max_se; in radv_emit_thread_trace_stop() local
277 for (unsigned se = 0; se < max_se; se++) { in radv_emit_thread_trace_stop()
405 unsigned max_se = device->physical_device->rad_info.max_se; in radv_thread_trace_init_bo() local
417 size = align64(sizeof(struct ac_thread_trace_info) * max_se, 1 << SQTT_BUFFER_ALIGN_SHIFT); in radv_thread_trace_init_bo()
418 size += device->thread_trace.buffer_size * (uint64_t)max_se; in radv_thread_trace_init_bo()
664 unsigned max_se = rad_info->max_se; in radv_get_thread_trace() local
669 for (unsigned se = 0; se < max_se; se++) { in radv_get_thread_trace()
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| D | si_cmd_buffer.c | 40 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1); in si_write_harvested_raster_configs()
842 if (cmd_buffer->device->physical_device->rad_info.max_se < 4 || in si_get_ia_multi_vgt_param()
861 if (gfx_level <= GFX8 && info->max_se == 4 && multi_instances_smaller_than_primgroup) in si_get_ia_multi_vgt_param()
871 if (info->max_se > 2 && !wd_switch_on_eop) in si_get_ia_multi_vgt_param()
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| D | radv_perfcounter.c | 366 ((ac_block->b->b->flags & AC_PC_BLOCK_SE) ? pdevice->rad_info.max_se : 1); in radv_pc_get_num_instances()
546 se_end = cmd_buffer->device->physical_device->rad_info.max_se; in radv_pc_sample_block()
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| D | radv_shader.c | 1238 unsigned max_se = pdevice->rad_info.max_se; in radv_consider_culling() local
1240 if (max_render_backends / max_se == 4) in radv_consider_culling()
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| D | radv_pipeline.c | 2718 unsigned num_se = pdevice->rad_info.max_se; in radv_pipeline_init_gs_ring_state()
5296 util_logbase2_ceil(pdevice->rad_info.max_render_backends / pdevice->rad_info.max_se); in radv_gfx9_compute_bin_size()
5297 unsigned log_num_se = util_logbase2_ceil(pdevice->rad_info.max_se); in radv_gfx9_compute_bin_size()
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| D | radv_device.c | 2327 properties->shaderEngineCount = pdevice->rad_info.max_se; in radv_GetPhysicalDeviceProperties2()
4126 tf_ring_size /= device->physical_device->rad_info.max_se; in radv_emit_tess_factor_ring()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_sqtt.c | 42 unsigned max_se = rad_info->max_se; in ac_thread_trace_get_data_offset() local
45 data_offset = align64(sizeof(struct ac_thread_trace_info) * max_se, in ac_thread_trace_get_data_offset()
94 uint32_t dropped_cntr_per_se = info->gfx10_dropped_cntr / rad_info->max_se; in ac_get_expected_buffer_size()
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| D | ac_gpu_info.c | 904 info->max_se = device_info.num_shader_engines; in ac_query_gpu_info()
1054 info->gfx_level >= GFX10 || (info->gfx_level >= GFX8 && info->max_se >= 2); in ac_query_gpu_info()
1070 info->gfx_level >= GFX8 && info->gfx_level <= GFX9 && info->max_se >= 2; in ac_query_gpu_info()
1141 for (i = 0; i < info->max_se; i++) { in ac_query_gpu_info()
1168 if (info->gfx_level >= GFX10_3 && info->max_se > 1) { in ac_query_gpu_info()
1171 for (unsigned se = 0; se < info->max_se; se++) { in ac_query_gpu_info()
1181 info->num_se = info->max_se; in ac_query_gpu_info()
1262 info->pbb_max_alloc_count = MIN2(128, pc_lines / (4 * info->max_se)); in ac_query_gpu_info()
1549 for (unsigned i = 0; i < info->max_se; i++) { in ac_print_gpu_info()
1559 fprintf(f, " max_se = %i\n", info->max_se); in ac_print_gpu_info()
[all …]
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| D | ac_perfcounter.c | 1079 groups_se = info->max_se; in ac_init_block_names()
1199 block->num_instances = info->max_se; in ac_init_perfcounters()
1203 block->num_instances = MAX2(1, info->max_se / 2); in ac_init_perfcounters()
1217 block->num_groups *= info->max_se; in ac_init_perfcounters()
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| D | ac_gpu_info.h | 203 uint32_t max_se; /* number of shader engines incl. disabled ones */ member
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| D | ac_rgp.c | 468 chunk->shader_engines = rad_info->max_se; in ac_sqtt_fill_asic_info()
503 chunk->prims_per_clock = rad_info->max_se; in ac_sqtt_fill_asic_info()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_sqtt.c | 43 unsigned max_se = sctx->screen->info.max_se; in si_thread_trace_init_bo() local
54 size = align64(sizeof(struct ac_thread_trace_info) * max_se, in si_thread_trace_init_bo()
56 size += sctx->thread_trace->buffer_size * (uint64_t)max_se; in si_thread_trace_init_bo()
85 unsigned max_se = sscreen->info.max_se; in si_emit_thread_trace_start() local
89 for (unsigned se = 0; se < max_se; se++) { in si_emit_thread_trace_start()
289 unsigned max_se = sctx->screen->info.max_se; in si_emit_thread_trace_stop() local
314 for (unsigned se = 0; se < max_se; se++) { in si_emit_thread_trace_stop()
533 unsigned max_se = sctx->screen->info.max_se; in si_get_thread_trace() local
536 thread_trace->num_traces = max_se; in si_get_thread_trace()
547 for (unsigned se = 0; se < max_se; se++) { in si_get_thread_trace()
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| D | si_state_binning.c | 47 util_logbase2_ceil(sscreen->info.max_render_backends / sscreen->info.max_se); in si_find_bin_size()
48 unsigned log_num_se = util_logbase2_ceil(sscreen->info.max_se); in si_find_bin_size()
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| D | si_perfcounter.c | 349 se_end = sctx->screen->info.max_se; in si_pc_query_suspend()
474 sub_gids = sub_gids * screen->info.max_se; in get_group_state()
574 instances = screen->info.max_se; in si_create_batch_query()
617 counter->qwords = screen->info.max_se; in si_create_batch_query()
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| D | si_state_draw.cpp | 628 bool has_primid_instancing_bug = sctx->gfx_level == GFX6 && sctx->screen->info.max_se == 1; in si_emit_derived_tess_state()
706 if (!sctx->screen->info.has_distributed_tess && sctx->screen->info.max_se > 1) in si_emit_derived_tess_state()
932 if (sscreen->info.max_se <= 2 || key->u.prim == PIPE_PRIM_POLYGON || in si_get_init_multi_vgt_param()
953 if (sscreen->info.gfx_level <= GFX8 && sscreen->info.max_se == 4 && in si_get_init_multi_vgt_param()
958 if (sscreen->info.max_se == 4 && !wd_switch_on_eop) in si_get_init_multi_vgt_param()
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| D | si_pipe.c | 1120 sscreen->se_tile_repeat = 32 * sscreen->info.max_se; in radeonsi_screen_create_impl()
1405 unsigned attr_ring_size = attr_ring_size_per_se * sscreen->info.max_se; in radeonsi_screen_create_impl()
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| D | si_state.c | 5493 assert(se == ~0 || se < sctx->screen->info.max_se); in si_set_grbm_gfx_index_se()
5503 unsigned num_se = MAX2(sctx->screen->info.max_se, 1); in si_write_harvested_raster_configs()
5941 sscreen->info.max_se) >> 16) - 1) | in si_init_cs_preamble_state()
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| D | si_query.c | 477 result->u32 = sctx->screen->info.max_se; in si_query_sw_get_result()
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| D | si_state_shaders.cpp | 3772 unsigned num_se = sctx->screen->info.max_se; in si_update_gs_ring_buffers()
4112 tf_ring_size_field /= sctx->screen->info.max_se; in si_init_tess_factor_ring()
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| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_winsys.c | 477 &ws->info.max_se); in do_winsys_init()
504 if (!ws->info.max_se) { in do_winsys_init()
507 ws->info.max_se = 1; in do_winsys_init()
516 ws->info.max_se = 2; in do_winsys_init()
519 ws->info.max_se = 4; in do_winsys_init()
524 ws->info.num_se = ws->info.max_se; in do_winsys_init()
531 (ws->info.max_se * ws->info.max_sa_per_se); in do_winsys_init()
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | r600_perfcounter.c | 173 se_end = ctx->screen->info.max_se; in r600_pc_query_emit_stop()
260 sub_gids = sub_gids * screen->info.max_se; in get_group_state()
368 instances = screen->info.max_se; in r600_create_batch_query()
415 counter->qwords = screen->info.max_se; in r600_create_batch_query()
442 groups_se = screen->info.max_se; in r600_init_block_names()
631 block->num_groups *= rscreen->info.max_se; in r600_perfcounters_add_block()
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| D | r600_pipe_common.c | 1316 printf("max_se = %i\n", rscreen->info.max_se); in r600_common_screen_init()
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| D | r600_query.c | 439 result->u32 = rctx->screen->info.max_se; in r600_query_sw_get_result()
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| D | r600_state_common.c | 1753 unsigned num_ses = rctx->screen->b.info.max_se; in r600_setup_scratch_area_for_shader()
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| /third_party/mesa3d/src/amd/vulkan/winsys/null/ |
| D | radv_null_winsys.c | 112 info->max_se = 4; in radv_null_winsys_query_info()
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