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Searched refs:mtc1 (Results 1 – 11 of 11) sorted by relevance

/third_party/libjpeg-turbo/simd/mips/
Djsimd_dspr2.S2847 mtc1 t1, f0
4210 mtc1 t1, f2
4211 mtc1 t2, f4
4212 mtc1 t3, f6
4213 mtc1 t4, f8
4214 mtc1 t5, f10
4215 mtc1 t6, f12
4216 mtc1 t7, f14
4217 mtc1 t8, f16
4253 mtc1 t1, f2
[all …]
/third_party/flutter/skia/third_party/externals/libjpeg-turbo/simd/mips/
Djsimd_dspr2.S2823 mtc1 t1, f0
4140 mtc1 t1, f2
4141 mtc1 t2, f4
4142 mtc1 t3, f6
4143 mtc1 t4, f8
4144 mtc1 t5, f10
4145 mtc1 t6, f12
4146 mtc1 t7, f14
4147 mtc1 t8, f16
4183 mtc1 t1, f2
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMipsInstrFPU.td194 def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
245 def MTC1_D64_MM : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>,
DMipsInstrFPU.td531 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
533 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
736 // This pseudo instr gets expanded into 2 mtc1 instrs after register
DMipsScheduleP5600.td562 // ctc1, mtc1, mthc1
DMicroMips32r6InstrInfo.td130 class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>;
706 class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
DMipsScheduleGeneric.td864 // ctc1, mtc1, mthc1, cfc1, mfc1, mfhc1
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.h233 void mtc1(const Operand *OpRt, const Operand *OpFs);
DIceAssemblerMIPS32.cpp804 mtc1(OpRs, OpRd); in move()
907 void AssemblerMIPS32::mtc1(const Operand *OpRt, const Operand *OpFs) { in mtc1() function in Ice::MIPS32::AssemblerMIPS32
DIceInstMIPS32.cpp929 Asm->mtc1(getSrc(0), getDest()); in emitIAS()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc4990 "mtc1\005dmtc2\006dmtgc0\004dmuh\005dmuhu\004dmul\005dmulo\006dmulou\005"
5054 "tc0\004mtc1\004mtc2\005mtgc0\005mthc0\005mthc1\005mthc2\006mthgc0\004mt"
7157 …{ 6684 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftF…
7158 …{ 6684 /* mtc1 */, Mips::MTC1_MMR6, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_Has…
7159 …{ 6684 /* mtc1 */, Mips::MTC1_MM, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNot…
7160 …{ 6684 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64…
7161 …{ 6684 /* mtc1 */, Mips::MTC1_D64_MM, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_I…
10589 { 6684 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10590 { 6684 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10591 { 6684 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
[all …]