Home
last modified time | relevance | path

Searched refs:nir_iand_imm (Results 1 – 25 of 38) sorted by relevance

12

/third_party/mesa3d/src/intel/compiler/
Dbrw_nir_lower_alpha_to_coverage.c68 nir_iand_imm(b, nir_ushr(b, nir_imm_int(b, 0xfea80), in build_dither_mask()
69 nir_iand_imm(b, m, ~3)), in build_dither_mask()
72 nir_ssa_def *part_b = nir_iand_imm(b, m, 2); in build_dither_mask()
73 nir_ssa_def *part_c = nir_iand_imm(b, m, 1); in build_dither_mask()
Dbrw_nir_lower_shader_calls.c179 nir_ssa_def *cull_mask = nir_iand_imm(b, call->src[2].ssa, 0xff); in lower_shader_trace_ray_instr()
180 nir_ssa_def *sbt_offset = nir_iand_imm(b, call->src[3].ssa, 0xf); in lower_shader_trace_ray_instr()
181 nir_ssa_def *sbt_stride = nir_iand_imm(b, call->src[4].ssa, 0xf); in lower_shader_trace_ray_instr()
182 nir_ssa_def *miss_index = nir_iand_imm(b, call->src[5].ssa, 0xffff); in lower_shader_trace_ray_instr()
Dbrw_nir_rt_builder.h322 defs->num_dss_rt_stacks = nir_iand_imm(b, nir_channel(b, data, 5), 0xffff); in brw_nir_rt_load_globals_addr()
421 defs->valid = nir_i2b(b, nir_iand_imm(b, bitfield, 1u << 16)); in brw_nir_rt_load_mem_hit_from_addr()
428 defs->front_face = nir_i2b(b, nir_iand_imm(b, bitfield, 1 << 27)); in brw_nir_rt_load_mem_hit_from_addr()
429 defs->done = nir_i2b(b, nir_iand_imm(b, bitfield, 1 << 28)); in brw_nir_rt_load_mem_hit_from_addr()
856 nir_iand_imm(b, brw_nir_rt_load(b, leaf_addr, 4, 1, 32), (1 << 24) - 1); in brw_nir_rt_load_bvh_instance_leaf()
858 nir_iand_imm(b, in brw_nir_rt_load_bvh_instance_leaf()
Dbrw_nir_lower_rt_intrinsics.c240 sysval = nir_iand_imm(b, geometry_index_dw, BITFIELD_MASK(29)); in lower_rt_intrinsics_impl()
322 sysval = nir_i2b(b, nir_iand_imm(b, flags_dw, 1u << 30)); in lower_rt_intrinsics_impl()
Dbrw_nir_lower_ray_queries.c177 nir_ssa_def *old_level = nir_iand_imm(b, old_value, 0x3); in update_trace_ctrl_level()
243 nir_ssa_def *cull_mask = nir_iand_imm(b, intrin->src[3].ssa, 0xff); in lower_ray_query_intrinsic()
418 sysval = nir_iand_imm(b, geometry_index_dw, BITFIELD_MASK(29)); in lower_ray_query_intrinsic()
Dbrw_nir_lower_shading_rate_output.c84 nir_iand_imm(b, bit_field, 0x3))); in lower_shading_rate_output_instr()
/third_party/mesa3d/src/amd/vulkan/
Dradv_meta_etc_decode.c138 nir_iand_imm(b, bit_offset, 31), nir_imm_int(b, 2)); in decode_etc2_alpha()
142 nir_iand_imm(b, bit_offset, 31), nir_imm_int(b, 1)); in decode_etc2_alpha()
255 nir_ssa_def *pixel_coord = nir_iand_imm(&b, nir_channels(&b, coord, 3), 3); in build_shader()
313 nir_iand_imm(&b, nir_ushr(&b, color_x, nir_iadd_imm(&b, linear_pixel, 15)), 2); in build_shader()
314 nir_ssa_def *lsb = nir_iand_imm(&b, nir_ushr(&b, color_x, linear_pixel), 1); in build_shader()
324 nir_iand_imm(&b, in build_shader()
353 nir_iand_imm(&b, color_y, 1)); in build_shader()
379 nir_iand_imm(&b, nir_ushr_imm(&b, color_y, 20), 1)); in build_shader()
381 nir_iand_imm(&b, nir_ushr_imm(&b, color_y, 16), 8)); in build_shader()
385 nir_ssa_def *da = nir_iand_imm(&b, color_y, 4); in build_shader()
[all …]
Dradv_pipeline_rt.c491 nir_iand_imm(&b_shader, intr->src[2].ssa, 0xff), 0x1); in lower_rt_instructions()
493 nir_iand_imm(&b_shader, intr->src[3].ssa, 0xf), 0x1); in lower_rt_instructions()
495 nir_iand_imm(&b_shader, intr->src[4].ssa, 0xf), 0x1); in lower_rt_instructions()
497 nir_iand_imm(&b_shader, intr->src[5].ssa, 0xffff), 0x1); in lower_rt_instructions()
579 ret = nir_iand_imm(&b_shader, ret, 0xFFFFFF); in lower_rt_instructions()
588 ret = nir_iand_imm(&b_shader, ret, 0xFFFFFFF); in lower_rt_instructions()
1158 nir_ssa_def *geometry_id = nir_iand_imm(b, geometry_id_and_flags, 0xfffffff); in insert_traversal_triangle_case()
1173 nir_iand_imm(b, nir_load_var(b, trav_vars->sbt_offset_and_flags), 0xffffff)), in insert_traversal_triangle_case()
1249 nir_ssa_def *geometry_id = nir_iand_imm(b, geometry_id_and_flags, 0xfffffff); in insert_traversal_aabb_case()
1267 nir_iand_imm(b, nir_load_var(b, trav_vars->sbt_offset_and_flags), 0xffffff)), in insert_traversal_aabb_case()
[all …]
Dradv_nir_lower_ray_queries.c346 rq_store_var(b, index, vars->cull_mask, nir_iand_imm(b, instr->src[3].ssa, 0xff), 0x1); in lower_rq_initialize()
405 return nir_iand_imm( in lower_rq_load()
411 return nir_iand_imm( in lower_rq_load()
420 return nir_iand_imm( in lower_rq_load()
706 nir_push_if(b, nir_ine_imm(b, nir_iand_imm(b, bvh_node_type, 4), 0)); in lower_rq_proceed()
709 nir_push_if(b, nir_ine_imm(b, nir_iand_imm(b, bvh_node_type, 2), 0)); in lower_rq_proceed()
712 nir_push_if(b, nir_ine_imm(b, nir_iand_imm(b, bvh_node_type, 1), 0)); in lower_rq_proceed()
752 nir_iand_imm(b, nir_channel(b, instance_data, 0), 63), 0x1); in lower_rq_proceed()
Dradv_device_generated_commands.c236 len = nir_iand_imm(b, len, 0x3fff); in nir_pkt3()
255 nir_pkt3(b, PKT3_SET_SH_REG, pkt_cnt), nir_iand_imm(b, vtx_base_sgpr, 0x3FFF), first_vertex, in dgc_emit_userdata_vertex()
384 nir_ssa_def *vbo_cnt = nir_iand_imm(&b, load_param8(&b, vbo_cnt), 0x7F); in build_dgc_prepare_shader()
420 &b, stream_base, nir_iand_imm(&b, nir_channel(&b, vbo_over_data, 0), 0x7FFF)); in build_dgc_prepare_shader()
509 rsrc_word3 = nir_iand_imm(&b, rsrc_word3, C_008F0C_OOB_SELECT); in build_dgc_prepare_shader()
513 nir_ssa_def *va_hi = nir_iand_imm(&b, nir_unpack_64_2x32_split_y(&b, va), 0xFFFF); in build_dgc_prepare_shader()
514 stride = nir_iand_imm(&b, stride, 0x3FFF); in build_dgc_prepare_shader()
527 nir_ssa_def *buf_va = nir_iand_imm( in build_dgc_prepare_shader()
736 state = nir_iand_imm(&b, state, 1); in build_dgc_prepare_shader()
823 nir_ssa_def *index_size = nir_iand_imm( in build_dgc_prepare_shader()
Dradv_meta_copy_vrs_htile.c105 nir_ssa_def *y_rate = nir_iand_imm(&b, nir_channel(&b, &tex->dest.ssa, 0), 3); in build_copy_vrs_htile_shader()
123 nir_store_var(&b, htile_value, nir_iand_imm(&b, input_value, 0xfffff33f), 0x1); in build_copy_vrs_htile_shader()
Dradv_rt_common.c345 return nir_iand_imm(b, node, (bvh_size - 1) << 3); in build_addr_to_node()
351 nir_ssa_def *addr = nir_iand_imm(b, node, ~7ull); in build_node_to_addr()
Dradv_nir_apply_pipeline_layout.c339 comp[6] = nir_iand_imm(b, comp[6], C_00A018_WRITE_COMPRESS_ENABLE); in get_sampler_desc()
350 comp[0] = nir_iand_imm(b, comp[0], C_008F30_TRUNC_COORD); in get_sampler_desc()
Dradv_acceleration_structure.c1430 nir_ssa_def *node_type = nir_iand_imm(b, node_id, 7); in determine_bounds()
1432 nir_iadd(b, node_addr, nir_u2u64(b, nir_ishl_imm(b, nir_iand_imm(b, node_id, ~7u), 3))); in determine_bounds()
1490 x = nir_iand_imm(b, nir_imul_imm(b, x, 0x00000101u), 0x0F00F00Fu); in build_morton_component()
1491 x = nir_iand_imm(b, nir_imul_imm(b, x, 0x00000011u), 0xC30C30C3u); in build_morton_component()
1492 x = nir_iand_imm(b, nir_imul_imm(b, x, 0x00000005u), 0x49249249u); in build_morton_component()
1593 nir_ssa_def *src_node_count = nir_iand_imm(&b, nir_channel(&b, pconst1, 3), 0x7FFFFFFFU); in build_internal_shader()
1595 nir_ine_imm(&b, nir_iand_imm(&b, nir_channel(&b, pconst1, 3), 0x80000000U), 0); in build_internal_shader()
1833 &b, nir_iand_imm(&b, instance_offset, sizeof(struct radv_bvh_instance_node) - 1), 0); in build_copy_shader()
Dradv_nir_lower_abi.c180 …return nir_imul_imm(b, nir_iand_imm(b, ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_tg_info), 0… in lower_abi_instr()
/third_party/mesa3d/src/microsoft/vulkan/
Ddzn_nir.c411 … old_index_size == 2 ? nir_iand_imm(&b, old_index_offset, ~3ULL) : old_index_offset, in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader()
416 nir_iand_imm(&b, index_val, 0xffff)); in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader()
426 … old_index_size == 2 ? nir_iand_imm(&b, old_index_offset, ~3ULL) : old_index_offset, in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader()
430 nir_iand_imm(&b, nir_channel(&b, index12, 0), 0xffff), in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader()
432 nir_iand_imm(&b, nir_channel(&b, index12, 1), 0xffff), in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader()
512 … old_index_size == 2 ? nir_iand_imm(&b, old_index0_offset, ~3ULL) : old_index0_offset, in dzn_nir_triangle_fan_rewrite_index_shader()
518 nir_iand_imm(&b, old_index0, 0xffff)); in dzn_nir_triangle_fan_rewrite_index_shader()
523 … old_index_size == 2 ? nir_iand_imm(&b, old_index1_offset, ~3ULL) : old_index1_offset, in dzn_nir_triangle_fan_rewrite_index_shader()
527 nir_iand_imm(&b, nir_channel(&b, old_index12, 0), 0xffff), in dzn_nir_triangle_fan_rewrite_index_shader()
529 nir_iand_imm(&b, nir_channel(&b, old_index12, 1), 0xffff), in dzn_nir_triangle_fan_rewrite_index_shader()
/third_party/mesa3d/src/panfrost/lib/
Dpan_indirect_draw.c383 nir_ior(b, nir_iand_imm(b, draw_w0, 0xffff), in update_dcd()
468 *d = nir_iand_imm(b, nir_u2u32(b, fi), ~(1 << 31)); in split_div()
488 w0 = nir_iand_imm(b, nir_channel(b, w01, 0), ~type_mask); in update_vertex_attrib_buf()
691 nir_iand_imm(b, nir_iadd_imm(b, size, 63), ~63); in update_varying_buf()
769 return nir_iand_imm(b, nir_iadd_imm(b, val, pot - 1), ~(pot - 1)); in nir_align_pot()
823 val = nir_ior(b, nir_iand_imm(b, val, 0xffffff01), in set_null_job()
858 nir_ssa_def *offset = nir_iand_imm(b, nir_unpack_64_2x32_split_x(b, base), 3); in get_instance_size()
862 nir_ssa_def *aligned_end = nir_iand_imm(b, end, ~3); in get_instance_size()
882 nir_ssa_def *data = nir_iand_imm(b, val, mask); in get_instance_size()
907 nir_ssa_def *data = nir_iand_imm(b, val, mask); in get_instance_size()
[all …]
Dpan_indirect_dispatch.c119 nir_ssa_def *num_wg_x_split = nir_iand_imm(&b, nir_ushr_imm(&b, split, 10), 0x3f); in GENX()
/third_party/mesa3d/src/compiler/nir/
Dnir_lower_ubo_vec4.c131 nir_iand_imm(b, in nir_lower_ubo_vec4_lower()
165 nir_iand_imm(b, in nir_lower_ubo_vec4_lower()
Dnir_opt_idiv_const.c116 return nir_isub(b, n, nir_iand_imm(b, tmp, -d)); in build_irem()
Dnir_format_convert.h457 mantissa = nir_iadd(b, nir_iand_imm(b, mantissa, 1), in nir_format_pack_r9g9b9e5()
/third_party/mesa3d/src/amd/common/
Dac_nir_lower_esgs_io_to_mem.c206 nir_ssa_def *cond = nir_i2b(b, nir_iand_imm(b, prim_id, 1)); in gs_get_vertex_offset()
249 return nir_iand_imm(b, vertex_offset, 0xffffu); in gs_per_vertex_input_vertex_offset_gfx9()
Dac_nir_lower_taskmesh_io_to_mem.c180 return nir_iand_imm(b, idx, s->num_entries - 1); in task_ring_entry_index()
230 return nir_iand_imm(b, nir_load_task_ring_entry_amd(b), s->num_entries - 1); in mesh_ring_entry_index()
/third_party/mesa3d/src/gallium/drivers/v3d/
Dv3d_blit.c696 nir_ishl(&b, nir_iand_imm(&b, x, 1), two); in v3d_get_sand8_fs()
698 nir_ishl(&b, nir_iand_imm(&b, x, 60), one); in v3d_get_sand8_fs()
708 nir_ishl(&b, nir_iand_imm(&b, x, 2), six), in v3d_get_sand8_fs()
716 nir_ishl(&b, nir_iand_imm(&b, x, 31), two)); in v3d_get_sand8_fs()
/third_party/mesa3d/src/panfrost/vulkan/
Dpanvk_vX_meta_copy.c382 rg = nir_iand_imm(&b, rg, 255); in panvk_meta_copy_img2img_shader()
925 nir_iand_imm(&b, texel, BITFIELD_MASK(5)), in panvk_meta_copy_buf2img_shader()
926 nir_iand_imm(&b, nir_ushr_imm(&b, texel, 5), BITFIELD_MASK(6)), in panvk_meta_copy_buf2img_shader()
927 nir_iand_imm(&b, nir_ushr_imm(&b, texel, 11), BITFIELD_MASK(5))); in panvk_meta_copy_buf2img_shader()
1412 nir_ishl(&b, nir_iand_imm(&b, nir_channel(&b, texel, i), 0xff), in panvk_meta_copy_img2buf_shader()

12