| /third_party/mesa3d/src/amd/common/ |
| D | ac_binary.c | 58 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8); in ac_parse_shader_binary_config()
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| D | ac_binary.h | 38 unsigned num_sgprs; member
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| D | ac_rtld.c | 536 config->num_sgprs = MAX2(config->num_sgprs, c.num_sgprs); in ac_rtld_read_config()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shader.c | 773 unsigned num_sgprs = BITSET_TEST(shader->selector->info.base.image_buffers, i) ? 4 : 8; in si_init_shader_args() local
775 while (ctx->args.num_sgprs_used % num_sgprs != 0) in si_init_shader_args()
778 ac_add_arg(&ctx->args, AC_ARG_SGPR, num_sgprs, AC_ARG_INT, &ctx->cs_image[i]); in si_init_shader_args()
1054 if (conf->num_sgprs) { in si_calculate_max_simd_waves()
1056 MIN2(max_simd_waves, sscreen->info.num_physical_sgprs_per_simd / conf->num_sgprs); in si_calculate_max_simd_waves()
1088 conf->num_sgprs, conf->num_vgprs, si_get_shader_binary_size(screen, shader), in si_shader_dump_stats_for_shader_db()
1123 conf->num_sgprs, conf->num_vgprs, conf->spilled_sgprs, conf->spilled_vgprs, in si_shader_dump_stats()
1939 if (shader->config.num_sgprs > max_sgprs || shader->config.num_vgprs > max_vgprs) { in si_compile_shader()
1943 shader->config.num_sgprs, shader->config.num_vgprs, max_sgprs, max_vgprs); in si_compile_shader()
2424 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs); in si_fix_resource_usage()
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| D | si_compute.c | 99 out_config->num_sgprs = code_object->wavefront_sgpr_count; in code_object_to_config()
162 unsigned num_sgprs = BITSET_TEST(sel->info.base.image_buffers, i) ? 4 : 8; in si_create_compute_state_async() local
164 if (align(user_sgprs, num_sgprs) + num_sgprs > 16) in si_create_compute_state_async()
167 user_sgprs = align(user_sgprs, num_sgprs); in si_create_compute_state_async()
170 user_sgprs += num_sgprs; in si_create_compute_state_async()
207 shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8); in si_create_compute_state_async()
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| D | si_shader_llvm.c | 438 unsigned num_sgprs, num_vgprs; in si_build_wrapper_function() local
453 num_sgprs = 0; in si_build_wrapper_function()
464 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4; in si_build_wrapper_function()
471 while (gprs < num_sgprs + num_vgprs) { in si_build_wrapper_function()
498 ac_add_arg(&ctx->args, gprs < num_sgprs ? AC_ARG_SGPR : AC_ARG_VGPR, size, arg_type, NULL); in si_build_wrapper_function()
500 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs)); in si_build_wrapper_function()
501 assert(gprs + size <= num_sgprs + num_vgprs && in si_build_wrapper_function()
502 (gprs >= num_sgprs || gprs + size <= num_sgprs)); in si_build_wrapper_function()
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| D | si_state_shaders.cpp | 698 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) | in si_shader_ls()
752 (sscreen->info.gfx_level <= GFX9 ? S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) in si_shader_hs()
821 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) | in si_shader_es()
1120 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_gs()
1155 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) | in si_shader_gs()
1749 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_vs()
2016 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_ps()
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| D | si_state_draw.cpp | 2033 unsigned num_sgprs = MIN2(count, num_vbos_in_user_sgprs) * 4; in si_upload_and_prefetch_VB_descriptors() local
2035 radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, num_sgprs); in si_upload_and_prefetch_VB_descriptors()
2036 radeon_emit_array(sctx->vb_descriptor_user_sgprs, num_sgprs); in si_upload_and_prefetch_VB_descriptors()
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| D | si_descriptors.c | 2294 unsigned num_sgprs = 8; in si_emit_compute_shader_pointers() local
2299 num_sgprs = 4; in si_emit_compute_shader_pointers()
2302 radeon_emit_array(&desc->list[desc_offset], num_sgprs); in si_emit_compute_shader_pointers()
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| D | si_sqtt.c | 1061 record->shader_data[gl_shader_stage].sgpr_count = shader->config.num_sgprs; in si_sqtt_add_code_object()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_shader_args.c | 34 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs) in set_loc() argument
37 ud_info->num_sgprs = num_sgprs; in set_loc()
38 *sgpr_idx += num_sgprs; in set_loc()
42 set_loc_shader(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx, uint8_t num_sgprs) in set_loc_shader() argument
47 set_loc(ud_info, sgpr_idx, num_sgprs); in set_loc_shader()
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| D | radv_shader.c | 1661 unsigned num_sgprs = MAX2(config_in->num_sgprs, args->ac.num_sgprs_used + 2 + 3); in radv_postprocess_config() local
1671 config_out->num_sgprs = num_sgprs; in radv_postprocess_config()
1697 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8); in radv_postprocess_config()
2388 S_00B228_SGPRS((bin->num_sgprs - 1) / 8);
2396 uint32_t num_sgprs, argument
2410 part_binary->num_sgprs = num_sgprs;
2665 if (conf->num_sgprs && gfx_level < GFX10) {
2666 unsigned sgprs = align(conf->num_sgprs, gfx_level >= GFX8 ? 16 : 8);
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| D | radv_shader.h | 191 uint8_t num_sgprs; member
460 uint8_t num_sgprs; member
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| D | radv_cmd_buffer.c | 994 assert(loc->num_sgprs == 1); in radv_emit_userdata_address()
1215 radeon_check_space(device->ws, cs, 2 + loc->num_sgprs); in radv_emit_inline_push_consts()
1217 radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, loc->num_sgprs); in radv_emit_inline_push_consts()
1218 radeon_emit_array(cs, values, loc->num_sgprs); in radv_emit_inline_push_consts()
3301 assert(loc->num_sgprs == 2); in emit_prolog_inputs()
6745 assert(ring_entry_loc && ring_entry_loc->sgpr_idx != -1 && ring_entry_loc->num_sgprs == 1); in radv_cs_emit_dispatch_taskmesh_direct_ace_packet()
6783 assert(ring_entry_loc->sgpr_idx != -1 && ring_entry_loc->num_sgprs == 1); in radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet()
6784 assert(!xyz_dim_enable || (xyz_dim_loc->sgpr_idx != -1 && xyz_dim_loc->num_sgprs == 3)); in radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet()
6785 assert(!draw_id_enable || (draw_id_loc->sgpr_idx != -1 && draw_id_loc->num_sgprs == 1)); in radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet()
6939 assert(task_ib_loc->num_sgprs == 3); in radv_emit_userdata_task_ib_only()
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| D | radv_device_generated_commands.c | 59 *cmd_size += (2 + locs->shader_data[AC_UD_INLINE_PUSH_CONSTANTS].num_sgprs) * 4; in radv_get_sequence_size()
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| D | radv_pipeline.c | 6822 pipeline->vtx_emit_num = loc->num_sgprs; in radv_pipeline_init_shader_stages_state()
7526 s->value.u64 = shader->config.num_sgprs; in radv_GetPipelineExecutableStatisticsKHR()
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| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_interface.h | 62 uint32_t num_sgprs,
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| D | aco_interface.cpp | 312 config.num_sgprs, in aco_compile_vs_prolog()
357 config.num_sgprs, in aco_compile_ps_epilog()
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| D | aco_validate.cpp | 330 unsigned num_sgprs = 0; in validate_ir() local
370 if (num_sgprs < 2) in validate_ir()
371 sgpr[num_sgprs++] = op.tempId(); in validate_ir()
379 check(num_sgprs + (literal.isUndefined() ? 0 : 1) <= const_bus_limit, in validate_ir()
1029 op.physReg() + op.size() > program->config->num_sgprs && in validate_ra()
1060 def.physReg() + def.size() > program->config->num_sgprs && in validate_ra()
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| D | aco_optimizer.cpp | 702 unsigned num_sgprs = 0; in check_vop3_operands() local
711 if (num_sgprs < 2) in check_vop3_operands()
712 sgpr[num_sgprs++] = op.tempId(); in check_vop3_operands()
2152 unsigned num_sgprs = (op[0].type() == RegType::sgpr) + (op[1].type() == RegType::sgpr); in combine_ordering_test() local
2153 if (num_sgprs > (ctx.program->gfx_level >= GFX10 ? 2 : 1)) in combine_ordering_test()
2168 if (neg[0] || neg[1] || abs[0] || abs[1] || opsel || num_sgprs > 1) { in combine_ordering_test()
3080 unsigned num_sgprs = !!sgpr_ids[0] + !!sgpr_ids[1]; in apply_sgprs() local
3103 if (!info.is_extract() && num_sgprs && ctx.uses[sgpr_info_id] > 1 && !instr->isVOP3() && in apply_sgprs()
3109 if (new_sgpr && num_sgprs >= max_sgprs) in apply_sgprs()
3137 sgpr_ids[num_sgprs++] = sgpr.id(); in apply_sgprs()
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| D | aco_register_allocation.cpp | 3087 program->config->num_sgprs = get_sgpr_alloc(program, ctx.max_used_sgpr + 1); in register_allocation()
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| D | aco_instruction_selection.cpp | 12366 unsigned num_sgprs = 0; in select_vs_prolog() local
12371 num_sgprs = MAX2(num_sgprs, desc.advance(num_descs * 16u).reg()); in select_vs_prolog()
12523 program->config->num_sgprs = get_sgpr_alloc(program, num_sgprs); in select_vs_prolog()
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| /third_party/mesa3d/src/amd/vulkan/layers/ |
| D | radv_sqtt_layer.c | 904 record->shader_data[i].sgpr_count = shader->config.num_sgprs; in radv_add_code_object()
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