| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrFormats.td | 113 bits<6> op3;
117 let Inst{24-19} = op3;
130 let op3 = op3val;
149 let op3 = op3val;
162 let op3 = op3val;
175 let op3 = op3val;
189 let op3 = op3val;
203 let op3 = op3val;
218 let op3 = op3val;
239 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern,
[all …]
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| /third_party/cmsis/CMSIS/Core/Include/ |
| D | cmsis_armclang_ltm.h | 1696 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) in __USADA8() argument
1700 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __USADA8()
1766 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLAD() argument
1770 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLAD()
1774 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLADX() argument
1778 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLADX()
1832 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLSD() argument
1836 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLSD()
1840 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLSDX() argument
1844 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLSDX()
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| D | cmsis_gcc.h | 1941 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) in __USADA8() argument
1945 __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __USADA8()
2036 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLAD() argument
2040 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLAD()
2044 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLADX() argument
2048 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLADX()
2102 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLSD() argument
2106 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLSD()
2110 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLSDX() argument
2114 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLSDX()
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| D | cmsis_armclang.h | 1491 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) in __SMMLA() argument
1495 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()
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| /third_party/vk-gl-cts/external/vulkancts/modules/vulkan/spirv_assembly/ |
| D | vktSpvAsmTrinaryMinMaxTests.cpp | 127 T min3(T op1, T op2, T op3) in min3() argument
129 return std::min({op1, op2, op3}); in min3()
133 T max3(T op1, T op2, T op3) in max3() argument
135 return std::max({op1, op2, op3}); in max3()
139 T mid3(T op1, T op2, T op3) in mid3() argument
141 std::array<T, 3> aux{{op1, op2, op3}}; in mid3()
358 char* op3 = inputByte + m_operandSize * 2u; in calculateResult() local
366 reinterpret_cast<void*>(op3)); in calculateResult()
371 op3 += m_componentSize; in calculateResult()
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| /third_party/vk-gl-cts/external/vulkancts/modules_no_buildgn/vulkan/spirv_assembly/ |
| D | vktSpvAsmTrinaryMinMaxTests.cpp | 127 T min3(T op1, T op2, T op3) in min3() argument
129 return std::min({op1, op2, op3}); in min3()
133 T max3(T op1, T op2, T op3) in max3() argument
135 return std::max({op1, op2, op3}); in max3()
139 T mid3(T op1, T op2, T op3) in mid3() argument
141 std::array<T, 3> aux{{op1, op2, op3}}; in mid3()
358 char* op3 = inputByte + m_operandSize * 2u; in calculateResult() local
366 reinterpret_cast<void*>(op3)); in calculateResult()
371 op3 += m_componentSize; in calculateResult()
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| /third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/source/opt/ |
| D | amd_ext_to_khr.cpp | 77 uint32_t op3 = inst->GetSingleWordInOperand(4); in ReplaceTrinaryMinMax() local
87 new_operands.push_back({SPV_OPERAND_TYPE_ID, {op3}}); in ReplaceTrinaryMinMax()
114 uint32_t op3 = inst->GetSingleWordInOperand(4); in ReplaceTrinaryMid() local
118 {op2, op3}); in ReplaceTrinaryMid()
121 {op2, op3}); in ReplaceTrinaryMid()
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| /third_party/skia/third_party/externals/spirv-tools/source/opt/ |
| D | amd_ext_to_khr.cpp | 77 uint32_t op3 = inst->GetSingleWordInOperand(4); in ReplaceTrinaryMinMax() local
87 new_operands.push_back({SPV_OPERAND_TYPE_ID, {op3}}); in ReplaceTrinaryMinMax()
114 uint32_t op3 = inst->GetSingleWordInOperand(4); in ReplaceTrinaryMid() local
118 {op2, op3}); in ReplaceTrinaryMid()
121 {op2, op3}); in ReplaceTrinaryMid()
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| /third_party/spirv-tools/source/opt/ |
| D | amd_ext_to_khr.cpp | 77 uint32_t op3 = inst->GetSingleWordInOperand(4); in ReplaceTrinaryMinMax() local
87 new_operands.push_back({SPV_OPERAND_TYPE_ID, {op3}}); in ReplaceTrinaryMinMax()
114 uint32_t op3 = inst->GetSingleWordInOperand(4); in ReplaceTrinaryMid() local
118 {op2, op3}); in ReplaceTrinaryMid()
121 {op2, op3}); in ReplaceTrinaryMid()
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| /third_party/ffmpeg/libavcodec/ppc/ |
| D | me_cmp.c | 444 register vector signed short op3 = vec_perm(but2, but2, perm3); \ in hadamard8_diff8x8_altivec()
445 res = vec_mladd(but2, vprod3, op3); \ in hadamard8_diff8x8_altivec()
612 register vector signed short op3 __asm__ ("v29") = \ in hadamard8_diff16x8_altivec()
616 res1 = vec_mladd(but2, vprod3, op3); \ in hadamard8_diff16x8_altivec()
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| /third_party/libdrm/freedreno/kgsl/ |
| D | msm_kgsl.h | 383 unsigned int op3; member
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_nir_lower_tess_io.cpp | 104 r600_umad_24(nir_builder *b, nir_ssa_def *op1, nir_ssa_def *op2, nir_ssa_def *op3) in r600_umad_24() argument
106 return nir_build_alu(b, nir_op_umad24, op1, op2, op3, NULL); in r600_umad_24()
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| /third_party/json/test/src/ |
| D | unit-json_patch.cpp | 47 json op3 = R"({ "value": "foo", "path": "/a/b/c", "op": "add" })"_json; variable
51 CHECK(op1 == op3);
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| /third_party/skia/third_party/externals/spirv-cross/ |
| D | spirv_glsl.hpp | 632 uint32_t op3, const char *op);
652 uint32_t op3, const char *op, SPIRType::BaseType offset_count_type);
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| D | spirv_glsl.cpp | 6077 uint32_t op2, uint32_t op3, const char *op) in emit_quaternary_func_op() argument
6079 …forward = should_forward(op0) && should_forward(op1) && should_forward(op2) && should_forward(op3); in emit_quaternary_func_op()
6082 to_unpacked_expression(op2), ", ", to_unpacked_expression(op3), ")"), in emit_quaternary_func_op()
6088 inherit_expression_dependencies(result_id, op3); in emit_quaternary_func_op()
6092 uint32_t op2, uint32_t op3, const char *op, in emit_bitfield_insert_op() argument
6097 …forward = should_forward(op0) && should_forward(op1) && should_forward(op2) && should_forward(op3); in emit_bitfield_insert_op()
6102 auto op3_expr = to_unpacked_expression(op3); in emit_bitfield_insert_op()
6114 if (expression_type(op3).basetype != offset_count_type) in emit_bitfield_insert_op()
6126 inherit_expression_dependencies(result_id, op3); in emit_bitfield_insert_op()
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| /third_party/mesa3d/src/freedreno/vulkan/ |
| D | msm_kgsl.h | 685 unsigned int op3; member
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| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_peephole.cpp | 2640 Value *op3[2] = { NULL, NULL }; in split64MulMad() local
2643 bld.mkSplit(op3, 4, i->getSrc(2)); in split64MulMad()
2645 op3[0] = i->getSrc(2); in split64MulMad()
2646 op3[1] = zero; in split64MulMad()
2652 bld.mkOp3(OP_MAD, hTy, tmpRes1Hi, op1[1], op2[0], op3[1]); in split64MulMad()
2664 bld.mkOp3(OP_MAD, hTy, def[0], op1[0], op2[0], op3[0])->setFlagsDef(1, carry); in split64MulMad()
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| /third_party/ffmpeg/libavcodec/aarch64/ |
| D | hevcdsp_idct_neon.S | 400 .macro add_member in, t0, t1, t2, t3, t4, t5, t6, t7, op0, op1, op2, op3, op4, op5, op6, op7, p
404 sum_sub v24.4s, \in, \t3, \op3, \p
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| /third_party/mesa3d/src/compiler/glsl/ |
| D | ir.cpp | 188 ir_rvalue *op2, ir_rvalue *op3) in ir_expression() argument
196 this->operands[3] = op3; in ir_expression()
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| D | ir.h | 1542 ir_rvalue *op2 = NULL, ir_rvalue *op3 = NULL);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | VOP3Instructions.td | 511 Instruction inst, SDPatternOperator op3> {
527 Instruction inst, SDPatternOperator op3> {
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| /third_party/glslang/SPIRV/ |
| D | SpvBuilder.cpp | 2546 Id Builder::createTriOp(Op opCode, Id typeId, Id op1, Id op2, Id op3) in createTriOp() argument
2554 operands[2] = op3; in createTriOp()
2561 op->addIdOperand(op3); in createTriOp()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 1675 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1678 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
1686 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1689 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
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| /third_party/ffmpeg/libavcodec/x86/ |
| D | vp3dsp.asm | 485 SHIFT(m3) ; xmm3 = op3
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/lib/Demangle/ |
| D | ItaniumDemangle.cpp | 3259 auto op3 = db.names.back().move_full(); in parse_expression() local
3264 db.names.back() = "(" + op1 + ") ? (" + op2 + ") : (" + op3 + ")"; in parse_expression()
|