Searched refs:op5 (Results 1 – 7 of 7) sorted by relevance
/third_party/libdrm/freedreno/kgsl/ |
D | msm_kgsl.h | 385 unsigned int op5; member
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/third_party/mesa3d/src/freedreno/vulkan/ |
D | msm_kgsl.h | 687 unsigned int op5; member
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/third_party/ffmpeg/libavcodec/aarch64/ |
D | hevcdsp_idct_neon.S | 400 .macro add_member in, t0, t1, t2, t3, t4, t5, t6, t7, op0, op1, op2, op3, op4, op5, op6, op7, p 406 sum_sub v26.4s, \in, \t5, \op5, \p
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMInstrFormats.td | 2113 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 2119 let Inst{7} = op5; // sx 2274 bit op5, bit op4, 2284 let Inst{5} = op5;
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D | ARMInstrVFP.td | 1676 bit op5, dag oops, dag iops, InstrItinClass itin, 1678 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> { 1687 bit op5, dag oops, dag iops, InstrItinClass itin, 1689 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
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D | ARMInstrMVE.td | 495 bit op5, bit op16, list<dag> pattern=[]> 505 let Inst{5} = op5; 517 class MVE_ScalarShiftDRegReg<string iname, bit op5, list<dag> pattern=[]> 520 "$RdaLo, $RdaHi, $Rm", op5, 0b0, pattern> { 525 class MVE_ScalarShiftDRegRegWithSat<string iname, bit op5, list<dag> pattern=[]> 528 "$RdaLo, $RdaHi, $sat, $Rm", op5, 0b1, pattern> {
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/third_party/ffmpeg/libavcodec/x86/ |
D | vp3dsp.asm | 490 SHIFT(m5) ; xmm5 = op5
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