Searched refs:pinning (Results 1 – 22 of 22) sorted by relevance
| /third_party/rust/crates/pin-utils/ |
| D | Cargo.toml | 11 Utilities for pinning
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| D | BUILD.gn | 26 cargo_pkg_description = "Utilities for pinning"
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| D | README.md | 3 Utilities for pinning
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| /third_party/libbpf/ci/vmtest/configs/ |
| D | ALLOWLIST-5.5.0 | 27 pinning
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| /third_party/node/doc/api/ |
| D | https.md | 369 Example pinning on certificate fingerprint, or the public key (similar to
392 // Pin the public key, similar to HPKP pin-sha25 pinning
414 // internet, while pinning the public key of the service in sensitive
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| /third_party/mesa3d/docs/relnotes/ |
| D | 20.3.3.rst | 101 - util: add AMD CPU family enums and enable L3 cache pinning on Zen3
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| D | 19.1.0.rst | 2962 - iris: move binder pinning outside the dirty == 0 check
2986 - iris: drop explicit pinning
3203 - iris: Fix compute scratch pinning
3306 - iris: Refactor depth/stencil buffer pinning into a helper.
3307 - iris: Fix write enable in pinning of depth/stencil resources
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| D | 20.3.0.rst | 3549 - st/mesa: remove random L3 pinning heuristic for glthread
3552 - util: completely rewrite and do AMD Zen L3 cache pinning correctly
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| D | 19.0.0.rst | 1723 - st/mesa: disable L3 thread pinning
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| D | 21.0.0.rst | 2275 - util: add AMD CPU family enums and enable L3 cache pinning on Zen3
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| D | 21.2.0.rst | 3421 - util: fix (re-enable) L3 cache pinning
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| D | 21.1.0.rst | 3654 - util: fix (re-enable) L3 cache pinning
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| D | 22.2.0.rst | 3418 - intel/compiler: Handle split-sends in EOT high-register pinning case
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| /third_party/libbpf/src/ |
| D | libbpf_internal.h | 258 __u32 pinning; member
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| D | linker.c | 1541 if (main_def->pinning != extra_def->pinning) { in map_defs_match()
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| D | libbpf.c | 2478 map_def->pinning = val;
2581 pr_debug("map '%s': found pinning = %u.\n", map->name, def->pinning);
2670 if (map_def.pinning == LIBBPF_PIN_BY_NAME) {
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| /third_party/skia/third_party/externals/opengl-registry/extensions/AMD/ |
| D | AMD_pinned_memory.txt | 157 RESOLVED: YES. Since the pinning of system memory is eventually handled
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| /third_party/openGLES/extensions/AMD/ |
| D | AMD_pinned_memory.txt | 157 RESOLVED: YES. Since the pinning of system memory is eventually handled
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| /third_party/mesa3d/docs/drivers/ |
| D | anv.rst | 27 effect on hardware that doesn't support soft-pinning (Ivybridge,
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| /third_party/rust/crates/clap/ |
| D | CHANGELOG.md | 2145 * **README.md:** adds guidance on when to use ~ in version pinning, and clarifies breaking change …
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| /third_party/openssl/ |
| D | CHANGES.md | 4195 trust-anchor "pinning", where the "pin" data takes the form
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| /third_party/icu/icu4j/perf-tests/data/collation/ |
| D | ulyss10.txt | 1988 He came to the table, pinning together his sheets. Stephen stood up.
27753 without saying, not contributing a copper or pinning his faith absolutely to
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