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Searched refs:radeon_set_uconfig_reg_seq (Results 1 – 11 of 11) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
Dradv_spm.c73 radeon_set_uconfig_reg_seq(cs, reg_base + b * 4, 1); in radv_emit_spm_counters()
89 radeon_set_uconfig_reg_seq(cs, regs->select0[c], 1); in radv_emit_spm_counters()
92 radeon_set_uconfig_reg_seq(cs, regs->select1[c], 1); in radv_emit_spm_counters()
Dradv_cs.h143 radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_uconfig_reg_seq() function
165 radeon_set_uconfig_reg_seq(cs, reg, 1); in radeon_set_uconfig_reg()
Dradv_perfcounter.c35 radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2); in radv_perfcounter_emit_shaders()
507 radeon_set_uconfig_reg_seq(cs, regs->select1[idx], 1); in radv_emit_select()
Dradv_sqtt.c359 radeon_set_uconfig_reg_seq(cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count); in radv_emit_thread_trace_userdata()
Dsi_cmd_buffer.c102 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2); in si_emit_compute()
Dradv_device.c4099 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2); in radv_emit_gs_ring_sizes()
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h181 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_uconfig_reg_seq() function
191 radeon_set_uconfig_reg_seq(cs, reg, 1); in radeon_set_uconfig_reg()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h137 #define radeon_set_uconfig_reg_seq(reg, num, perfctr) do { \ macro
145 radeon_set_uconfig_reg_seq(reg, 1, false); \
150 radeon_set_uconfig_reg_seq(reg, 1, true); \
Dsi_perfcounter.c91 radeon_set_uconfig_reg_seq(R_036780_SQ_PERFCOUNTER_CTRL, 2, false); in si_pc_emit_shaders()
113 radeon_set_uconfig_reg_seq(regs->select0[idx], 1, false); in si_pc_emit_select()
118 radeon_set_uconfig_reg_seq(regs->select1[idx], 1, false); in si_pc_emit_select()
759 radeon_set_uconfig_reg_seq(reg_base + b * 4, 1, false); in si_emit_spm_counters()
775 radeon_set_uconfig_reg_seq(regs->select0[c], 1, false); in si_emit_spm_counters()
778 radeon_set_uconfig_reg_seq(regs->select1[c], 1, false); in si_emit_spm_counters()
Dsi_sqtt.c787 … radeon_set_uconfig_reg_seq(R_030D08_SQ_THREAD_TRACE_USERDATA_2, count, sctx->gfx_level >= GFX10); in si_emit_thread_trace_userdata()
Dsi_compute.c417 radeon_set_uconfig_reg_seq(R_030E00_TA_CS_BC_BASE_ADDR, 2, false); in si_emit_initial_compute_regs()