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Searched refs:regClass (Results 1 – 23 of 23) sorted by relevance

/third_party/mesa3d/src/amd/compiler/
Daco_validate.cpp234 instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed())) in validate_ir()
237 if (instr->definitions[0].regClass().is_subdword() && !instr->definitions[0].isFixed()) in validate_ir()
243 check(instr->definitions[0].regClass() == in validate_ir()
250 instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed()) in validate_ir()
254 check(instr->definitions[0].regClass() == v1, "VOP3P must have v1 definition", in validate_ir()
278 if (instr->definitions[i].regClass().is_subdword()) in validate_ir()
337 check(i != 1 || (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
340 check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr && in validate_ir()
347 check(i != 0 || (op.isTemp() && op.regClass().type() == RegType::vgpr), in validate_ir()
349 check(i == 0 || (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
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Daco_lower_to_hw_instr.cpp193 assert(instr->definitions[1].regClass() == bld.lm); in emit_vadd32()
513 if (src.regClass() == v1b) { in emit_reduction()
534 } else if (src.regClass() == v2b) { in emit_reduction()
815 if (reduction_needs_last_op && dst.regClass().type() == RegType::vgpr) { in emit_reduction()
828 if (dst.regClass().type() == RegType::sgpr) { in emit_reduction()
862 assert(dst.regClass() == v1); in emit_gfx10_wave64_bpermute()
863 assert(tmp_exec.regClass() == bld.lm); in emit_gfx10_wave64_bpermute()
865 assert(same_half.regClass() == bld.lm); in emit_gfx10_wave64_bpermute()
866 assert(index_x4.regClass() == v1); in emit_gfx10_wave64_bpermute()
867 assert(input_data.regClass().type() == RegType::vgpr); in emit_gfx10_wave64_bpermute()
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Daco_reindex_ssa.cpp44 RegClass rc = def.regClass(); in reindex_defs()
58 assert(op.regClass() == ctx.temp_rc[new_id]); in reindex_ops()
59 op.setTemp(Temp(new_id, op.regClass())); in reindex_ops()
91 program->private_segment_buffer.regClass()); in reindex_program()
93 Temp(ctx.renames[program->scratch_offset.id()], program->scratch_offset.regClass()); in reindex_program()
Daco_instruction_selection.cpp151 RegClass rc = RegClass(mask.regClass().type(), 1); in emit_mbcnt()
178 dst = bld.tmp(src.regClass()); in emit_wqm()
190 if (index.regClass() == s1) in emit_bpermute()
350 if (src.regClass() == dst_rc) { in emit_extract_vector()
358 if (it != ctx->allocated_vec.end() && dst_rc.bytes() == it->second[idx].regClass().bytes()) { in emit_extract_vector()
359 if (it->second[idx].regClass() == dst_rc) { in emit_extract_vector()
554 if (vec.regClass() == dst.regClass()) { in byte_align_vector()
610 assert(val.regClass() == s1); in bool_to_vector_condition()
611 assert(dst.regClass() == bld.lm); in bool_to_vector_condition()
624 assert(val.regClass() == bld.lm); in bool_to_scalar_condition()
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Daco_register_allocation.cpp65 rc = def.regClass(); in set()
327 if (op.regClass().is_subdword()) in fill()
333 void clear(Operand op) { clear(op.physReg(), op.regClass()); } in clear()
337 if (def.regClass().is_subdword()) in fill()
343 void clear(Definition def) { clear(def.physReg(), def.regClass()); } in clear()
829 copy.second.setTemp(ctx.program->allocateTmp(copy.second.regClass())); in update_renames()
830 ctx.assignments.emplace_back(copy.second.physReg(), copy.second.regClass()); in update_renames()
1072 instr->operands[i].regClass() == info.rc) { in get_reg_for_create_vector_copy()
1139 Definition pc_def = Definition(res.first, pc_op.regClass()); in get_regs_for_copies()
1228 Definition pc_def = Definition(reg_win.lo(), pc_op.regClass()); in get_regs_for_copies()
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Daco_lower_to_cssa.cpp103 if (def.regClass().type() == RegType::sgpr && !op.isTemp()) { in collect_parallelcopies()
118 Temp tmp = bld.tmp(def.regClass()); in collect_parallelcopies()
173 idom = b.regClass().type() == RegType::vgpr ? ctx.program->blocks[idom].logical_idom in dominates()
351 pred = copy.op.regClass().type() == RegType::vgpr ? ctx.program->blocks[pred].logical_idom in try_coalesce_copy()
359 if (copy.op.regClass() != copy.def.regClass()) in try_coalesce_copy()
393 if (cp.def.regClass().type() != type || it->second.num_uses > 0) { in emit_copies_block()
413 [&](auto& n) { return n.second.cp.def.regClass().type() == type; }); in emit_copies_block()
424 while (it->second.cp.def.regClass().type() != type) in emit_copies_block()
466 bool is_vgpr = cp.def.regClass().type() == RegType::vgpr; in emit_parallelcopies()
Daco_lower_phis.cpp318 if (phi->operands[i].regClass() == phi->definitions[0].regClass()) in lower_subdword_phis()
325 assert(phi_src.regClass().type() == RegType::sgpr); in lower_subdword_phis()
328 Temp new_phi_src = bld.tmp(phi->definitions[0].regClass()); in lower_subdword_phis()
347 assert(program->wave_size == 64 ? phi->definitions[0].regClass() != s1 in lower_phis()
348 : phi->definitions[0].regClass() != s2); in lower_phis()
349 if (phi->definitions[0].regClass() == program->lane_mask) in lower_phis()
351 else if (phi->definitions[0].regClass().is_subdword()) in lower_phis()
Daco_optimizer_postRA.cpp123 assert(def.regClass().type() != RegType::sgpr || def.physReg().reg() <= 255); in save_reg_writes()
124 assert(def.regClass().type() != RegType::vgpr || def.physReg().reg() >= 256); in save_reg_writes()
130 if (def.regClass().is_subdword()) in save_reg_writes()
134 assert(def.size() == dw_size || def.regClass().is_subdword()); in save_reg_writes()
162 return last_writer_idx(ctx, op.physReg(), op.regClass()); in last_writer_idx()
200 return is_clobbered_since(ctx, t.physReg(), t.regClass(), idx); in is_clobbered_since()
Daco_opt_value_numbering.cpp153 if (a->definitions[i].regClass() != b->definitions[i].regClass()) in operator ()()
394 instr->operands[0].regClass() == instr->definitions[0].regClass()) { in process_block()
410 assert(instr->definitions[i].regClass() == orig_instr->definitions[i].regClass()); in process_block()
Daco_reduce_assign.cpp102 reduceTmp = program->allocateTmp(reduceTmp.regClass()); in setup_reduce_temp()
144 vtmp = program->allocateTmp(vtmp.regClass()); in setup_reduce_temp()
Daco_spill.cpp205 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear()) in next_uses_per_block()
415 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear()) in update_local_next_uses()
561 spill_id = ctx.allocate_spill_id(to_spill.regClass()); in init_live_in_vars()
592 ctx.spills_entry[block_idx][to_spill] = ctx.allocate_spill_id(to_spill.regClass()); in init_live_in_vars()
716 ctx.allocate_spill_id(phi->definitions[0].regClass()); in init_live_in_vars()
746 ctx.spills_entry[block_idx][to_spill] = ctx.allocate_spill_id(to_spill.regClass()); in init_live_in_vars()
792 Temp new_name = ctx.program->allocateTmp(live.first.regClass()); in add_coupling_code()
827 Temp new_name = ctx.program->allocateTmp(live.first.regClass()); in add_coupling_code()
903 uint32_t spill_id = ctx.allocate_spill_id(phi->definitions[0].regClass()); in add_coupling_code()
1017 Temp new_name = ctx.program->allocateTmp(tmp.regClass()); in add_coupling_code()
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Daco_ir.h412 constexpr RegClass regClass() const noexcept { return (RegClass::RC)reg_class; } in regClass() function
414 constexpr unsigned bytes() const noexcept { return regClass().bytes(); } in bytes()
415 constexpr unsigned size() const noexcept { return regClass().size(); } in size()
416 constexpr RegType type() const noexcept { return regClass().type(); } in type()
417 constexpr bool is_linear() const noexcept { return regClass().is_linear(); } in is_linear()
744 constexpr RegClass regClass() const noexcept { return data_.temp.regClass(); } in regClass() function
826 return hasRegClass() && regClass().type() == type; in isOfType()
873 return other.isUndefined() && other.regClass() == regClass();
943 constexpr RegClass regClass() const noexcept { return temp.regClass(); } in regClass() function
Daco_optimizer.cpp543 [](const Definition& def) { return def.regClass().type() == RegType::vgpr; }); in pseudo_propagate_temp()
552 [](const Definition& def) { return def.regClass().is_subdword(); }); in pseudo_propagate_temp()
587 if (temp.regClass() == instr->definitions[0].regClass()) in pseudo_propagate_temp()
708 if (op.hasRegClass() && op.regClass().type() == RegType::sgpr) { in check_vop3_operands()
832 bitwise_instr->operands[1].isOfType(op.regClass().type())) in skip_smem_offset_align()
835 bitwise_instr->operands[0].isOfType(op.regClass().type())) in skip_smem_offset_align()
860 base.regClass() == s1 && offset <= 0xFFFFF && ctx.program->gfx_level >= GFX9 && in smem_combine()
1294 instr->operands[i] = Operand(instr->operands[i].regClass()); in label_instruction()
1296 while (info.is_temp() && info.temp.regClass() == instr->operands[i].getTemp().regClass()) { in label_instruction()
1437 base.regClass() == v1 && mubuf.offset + offset < 4096) { in label_instruction()
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Daco_insert_NOPs.cpp418 if (def.regClass().type() != RegType::sgpr) { in handle_instruction_gfx6()
449 if (!op.isConstant() && !op.isUndefined() && op.regClass().type() == RegType::sgpr) in handle_instruction_gfx6()
510 if (def.regClass().type() == RegType::sgpr) { in handle_instruction_gfx6()
548 instr->operands[1].regClass().type() == RegType::vgpr && in handle_instruction_gfx6()
Daco_insert_waitcnt.cpp251 instr->operands[1].regClass() == s4) in get_vmem_type()
610 insert_wait_entry(ctx, op.physReg(), op.regClass(), event, false, vmem_types); in insert_wait_entry()
616 insert_wait_entry(ctx, def.physReg(), def.regClass(), event, true, vmem_types); in insert_wait_entry()
Daco_print_ir.cpp169 print_reg_class(operand->regClass(), output); in aco_print_operand()
193 print_reg_class(definition->regClass(), output); in print_definition()
Daco_live_var_analysis.cpp98 instr->operands[2].regClass().type() == RegType::sgpr) in instr_needs_vcc()
Daco_insert_exec_mask.cpp181 return Operand(exec, t.regClass()); in get_exec_op()
511 data = bld.copy(bld.def(data.regClass()), data); in handle_atomic_data()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DFLATInstructions.td136 class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
140 (outs regClass:$vdst),
146 !if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
177 multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedInput = 0> {
179 def "" : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1>,
181 def _SADDR : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1, 1>,
186 multiclass FLAT_Global_Store_Pseudo<string opName, RegisterClass regClass> {
188 def "" : FLAT_Store_Pseudo<opName, regClass, 1>,
190 def _SADDR : FLAT_Store_Pseudo<opName, regClass, 1, 1>,
195 class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
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DSIWholeQuadMode.cpp862 const TargetRegisterClass *regClass = Register::isVirtualRegister(Reg) in lowerCopyInstrs() local
866 const unsigned MovOp = TII->getMovOpcode(regClass); in lowerCopyInstrs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h467 int16_t regClass = Desc.OpInfo[OpNo].RegClass; in getRegNumForOperand() local
468 switch (regClass) { in getRegNumForOperand()
/third_party/mesa3d/src/amd/compiler/tests/
Dhelpers.cpp343 return b.pseudo(aco_opcode::p_extract, b.def(src.regClass()), src, Operand::c32(idx), in ext_ushort()
349 return b.pseudo(aco_opcode::p_extract, b.def(src.regClass()), src, Operand::c32(idx), in ext_ubyte()
/third_party/mesa3d/docs/relnotes/
D20.1.0.rst1197 - aco: refactor regClass setup for subdword VGPRs