Searched refs:reg_index (Results 1 – 8 of 8) sorted by relevance
/third_party/pcre2/pcre2/src/sljit/ |
D | sljitNativeSPARC_32.c | 143 sljit_s32 reg_index = 8; in call_with_args() local 164 if (reg_index == reg || reg_index + 1 == reg) in call_with_args() 166 reg_index += 2; in call_with_args() 170 if (reg_index == reg) in call_with_args() 172 reg_index++; in call_with_args() 175 if (reg_index != word_reg_index && reg_index == reg) in call_with_args() 177 reg_index++; in call_with_args() 223 reg_index -= 2; in call_with_args() 224 if (reg_index < 14) { in call_with_args() 225 if ((reg_index & 0x1) != 0) { in call_with_args() [all …]
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D | sljitNativeSPARC_common.c | 515 sljit_s32 reg_index, types, tmp; in sljit_emit_enter() local 538 reg_index = 24; in sljit_emit_enter() 540 while (types && reg_index < 24 + 6) { in sljit_emit_enter() 543 if (reg_index & 0x1) { in sljit_emit_enter() 544 … FAIL_IF(push_inst(compiler, STW | DA(reg_index) | S1(SLJIT_SP) | IMM(float_offset), MOVABLE_INS)); in sljit_emit_enter() 545 if (reg_index >= 24 + 6 - 1) in sljit_emit_enter() 547 …FAIL_IF(push_inst(compiler, STW | DA(reg_index + 1) | S1(SLJIT_SP) | IMM(float_offset + sizeof(slj… in sljit_emit_enter() 549 … FAIL_IF(push_inst(compiler, STD | DA(reg_index) | S1(SLJIT_SP) | IMM(float_offset), MOVABLE_INS)); in sljit_emit_enter() 552 reg_index++; in sljit_emit_enter() 555 … FAIL_IF(push_inst(compiler, STW | DA(reg_index) | S1(SLJIT_SP) | IMM(float_offset), MOVABLE_INS)); in sljit_emit_enter() [all …]
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/third_party/mesa3d/src/amd/registers/ |
D | parse_kernel_headers.py | 820 reg_index = type_map.index(name) if name in type_map else -1 821 if reg_index >= 1 and reg_index % 2 == 1: 822 type_name = type_map[reg_index - 1]
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/third_party/mesa3d/src/gallium/drivers/radeonsi/ |
D | si_shader_llvm_vs.c | 388 unsigned reg_index; in si_llvm_clipvertex_to_clipdist() local 398 for (reg_index = 0; reg_index < 2; reg_index++) { in si_llvm_clipvertex_to_clipdist() 399 struct ac_export_args *args = &clipdist[reg_index]; in si_llvm_clipvertex_to_clipdist() 401 if (!(clipdist_mask & BITFIELD_RANGE(reg_index * 4, 4))) in si_llvm_clipvertex_to_clipdist() 408 if (!(clipdist_mask & BITFIELD_BIT(reg_index * 4 + chan))) in si_llvm_clipvertex_to_clipdist() 413 LLVMConstInt(ctx->ac.i32, ((reg_index * 4 + chan) * 4 + const_chan) * 4, 0); in si_llvm_clipvertex_to_clipdist() 424 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index; in si_llvm_clipvertex_to_clipdist()
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/third_party/mesa3d/src/gallium/drivers/r300/ |
D | r300_reg.h | 2946 #define PVS_OP_DST_OPERAND(opcode, math_inst, macro_inst, reg_index, reg_writemask, reg_class, satu… argument 2950 | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) \
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/third_party/mesa3d/src/amd/compiler/ |
D | aco_register_allocation.cpp | 889 auto is_free = [&](PhysReg reg_index) in get_reg_simple() 890 { return reg_file[reg_index] == 0 && !ctx.war_hint[reg_index]; }; in get_reg_simple() argument
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/third_party/mesa3d/src/gallium/auxiliary/gallivm/ |
D | lp_bld_tgsi_soa.c | 673 unsigned reg_file, unsigned reg_index, in get_indirect_index() argument 688 base = lp_build_const_int_vec(bld->bld_base.base.gallivm, uint_bld->type, reg_index); in get_indirect_index()
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/third_party/mesa3d/src/gallium/drivers/svga/ |
D | svga_tgsi_vgpu10.c | 6783 unsigned reg_index = emit->clip_dist_out_index + i / 4; in emit_clip_distance_from_vpos() local 6788 dst = make_dst_reg(TGSI_FILE_OUTPUT, reg_index); in emit_clip_distance_from_vpos() 6826 unsigned reg_index = emit->clip_dist_out_index + i / 4; in emit_clip_vertex_instructions() local 6831 dst = make_dst_reg(TGSI_FILE_OUTPUT, reg_index); in emit_clip_vertex_instructions()
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