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Searched refs:regclass (Results 1 – 20 of 20) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1992 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1993 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1997 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1998 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
2002 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
2003 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
2004 regclass:$dst4),
2011 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
2012 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
2014 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
[all …]
DNVPTXIntrinsics.td178 foreach regclass = ["i32", "f32"] in {
183 def : SHFL_INSTR<sync, mode, regclass, return_pred,
195 multiclass VOTE<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
196 def : NVPTXInst<(outs regclass:$dest), (ins Int1Regs:$pred),
198 [(set regclass:$dest, (IntOp Int1Regs:$pred))]>,
208 multiclass VOTE_SYNC<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
209 def i : NVPTXInst<(outs regclass:$dest), (ins i32imm:$mask, Int1Regs:$pred),
211 [(set regclass:$dest, (IntOp imm:$mask, Int1Regs:$pred))]>,
213 def r : NVPTXInst<(outs regclass:$dest), (ins Int32Regs:$mask, Int1Regs:$pred),
215 [(set regclass:$dest, (IntOp Int32Regs:$mask, Int1Regs:$pred))]>,
[all …]
/third_party/ltp/tools/sparse/sparse-src/
Dcompile-i386.c306 struct regclass { struct
311 static struct regclass regclass_8 = { "8-bit", { AL, DL, CL, BL, AH, DH, CH, BH }}; argument
312 static struct regclass regclass_16 = { "16-bit", { AX, DX, CX, BX, SI, DI, BP }};
313 static struct regclass regclass_32 = { "32-bit", { EAX, EDX, ECX, EBX, ESI, EDI, EBP }};
314 static struct regclass regclass_64 = { "64-bit", { EAX_EDX, ECX_EBX, ESI_EDI }};
316 static struct regclass regclass_32_8 = { "32-bit bytes", { EAX, EDX, ECX, EBX }};
318 static struct regclass *get_regclass_bits(int bits) in get_regclass_bits()
328 static struct regclass *get_regclass(struct expression *expr) in get_regclass()
350 static struct storage *get_reg(struct regclass *class) in get_reg()
365 static struct storage *get_reg_value(struct storage *value, struct regclass *class) in get_reg_value()
/third_party/mesa3d/docs/relnotes/
D20.0.3.rst145 - aco: fix boolean undef regclass
D20.2.0.rst3825 - aco: use Info::definition_size instead of definition's regclass
3854 - aco: use the same regclass as the definition for undef phi operands
3953 - aco: fix regclass checks when fixing to vcc/exec with Builder
D20.1.0.rst3535 - aco: fix boolean undef regclass
3599 - aco: make RegisterFile::block() take a regclass
D20.0.0.rst3410 - aco/wave32: Use lane mask regclass for exec/vcc.
D20.3.0.rst4004 - aco: fix regclass checks when fixing to vcc/exec with Builder
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrArithmetic.td539 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
554 RegisterClass RegClass = regclass;
657 // both a regclass and EFLAGS as a result.
665 // both a regclass and EFLAGS as a result, and has EFLAGS as input.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTarget.td700 /// type that it doesn't know, and resolves the actual regclass to use by using
813 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
816 RegisterClass RegClass = regclass;
1069 let InOperandList = (ins unknown:$src, i32imm:$regclass);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DTargetOpcodes.def89 // pair. Once it has been lowered to a MachineInstr, the regclass operand
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td237 // Condition code regclass.
DAArch64InstrFormats.td860 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
864 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
890 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
894 let MIOperandInfo = (ops regclass, shiftop);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenRegisterInfo.inc5497 assert(RC && "Missing regclass");
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenRegisterInfo.inc7137 assert(RC && "Missing regclass");
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc9595 assert(RC && "Missing regclass");
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td1496 // can be SP. We need another regclass (similar to rGPR) to represent
DARMInstrInfo.td2399 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenRegisterInfo.inc15644 assert(RC && "Missing regclass");
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterInfo.inc20056 assert(RC && "Missing regclass");