| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineLoopUtils.cpp | 57 MO.setReg(R); in PeelSingleBlockLoop()
69 Use->setReg(R); in PeelSingleBlockLoop()
78 MO.setReg(Remaps[MO.getReg()]); in PeelSingleBlockLoop()
93 OrigPhi.getOperand(InitRegIdx).setReg(R); in PeelSingleBlockLoop()
100 MI.getOperand(LoopRegIdx).setReg(LoopReg); in PeelSingleBlockLoop()
|
| D | BreakFalseDeps.cpp | 136 MO.setReg(CurrMO.getReg()); in pickBestRegisterForUndef()
158 MO.setReg(MaxClearanceReg); in pickBestRegisterForUndef()
|
| D | ModuloSchedule.cpp | 344 O.setReg(ToReg); in replaceRegUsesAfterLoop()
1035 MO.setReg(NewReg); in updateInstruction()
1051 MO.setReg(VRMap[StageNum][reg]); in updateInstruction()
1185 UseOp.setReg(ReplaceReg); in rewriteScheduledInstr()
1324 MO.setReg(Reg); in rewrite()
1474 MI->getOperand(1).setReg(InitReg.getValue()); in phi()
1654 MI.getOperand(0).setReg(PhiReg); in moveStageBetweenBlocks()
1668 NewMI->getOperand(0).setReg(R); in moveStageBetweenBlocks()
1669 NewMI->getOperand(1).setReg(OrigR); in moveStageBetweenBlocks()
1682 MO.setReg(Remaps[MO.getReg()]); in moveStageBetweenBlocks()
[all …]
|
| D | TailDuplicator.cpp | 400 MO.setReg(NewReg); in duplicateInstruction()
431 MO.setReg(VI->second.Reg); in duplicateInstruction()
449 MO.setReg(NewReg); in duplicateInstruction()
520 MI.getOperand(Idx).setReg(SrcReg); in updateSuccessorsPHIs()
532 MI.getOperand(Idx).setReg(Reg); in updateSuccessorsPHIs()
|
| D | AntiDepBreaker.h | 62 MI.getOperand(0).setReg(NewReg); in UpdateDbgValue()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 246 MI.getOperand(0).setReg(KilledProdReg); in processBlock()
247 MI.getOperand(1).setReg(KilledProdReg); in processBlock()
248 MI.getOperand(3).setReg(AddendSrcReg); in processBlock()
265 MI.getOperand(2).setReg(AddendSrcReg); in processBlock()
270 MI.getOperand(2).setReg(OtherProdReg); in processBlock()
|
| D | PPCMIPeephole.cpp | 424 MI.getOperand(1).setReg(DefReg1); in simplifyCode()
425 MI.getOperand(2).setReg(DefReg2); in simplifyCode()
446 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
514 MI.getOperand(1).setReg(ShiftOp1); in simplifyCode()
556 Use.getOperand(i).setReg(ConvReg1); in simplifyCode()
616 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
660 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
918 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); in simplifyCode()
946 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); in simplifyCode()
1436 CMPI2->getOperand(1).setReg(Op2); in eliminateRedundantCompare()
[all …]
|
| D | PPCVSXCopy.cpp | 114 SrcMO.setReg(NewVReg); in processBlock()
133 SrcMO.setReg(NewVReg); in processBlock()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyDebugValueManager.cpp | 34 DBI->getOperand(0).setReg(Reg); in updateReg()
43 Clone->getOperand(0).setReg(NewReg); in clone()
|
| D | WebAssemblyPeephole.cpp | 67 MO.setReg(NewReg); in maybeRewriteToDrop()
123 MO.setReg(NewReg); in maybeRewriteToFallthrough()
|
| D | WebAssemblyExplicitLocals.cpp | 252 MI.getOperand(2).setReg(NewReg); in runOnMachineFunction()
303 MI.getOperand(0).setReg(NewReg); in runOnMachineFunction()
359 MO.setReg(NewReg); in runOnMachineFunction()
|
| D | WebAssemblyRegStackify.cpp | 503 Def->getOperand(0).setReg(NewReg); in moveForSingleUse()
504 Op.setReg(NewReg); in moveForSingleUse()
540 Op.setReg(NewReg); in rematerializeCheapDef()
617 Op.setReg(TeeReg); in moveAndTeeForMultiUse()
618 DefMO.setReg(DefReg); in moveAndTeeForMultiUse()
|
| D | WebAssemblyReplacePhysRegs.cpp | 93 MO.setReg(VReg); in runOnMachineFunction()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 381 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
392 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
404 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
416 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); in HexagonProcessInstruction()
542 MO.setReg(High); in HexagonProcessInstruction()
554 MO.setReg(High); in HexagonProcessInstruction()
568 MO.setReg(High); in HexagonProcessInstruction()
601 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1383 MO.setReg(matchRegister(Reg1)); in processInstruction()
1398 MO.setReg(matchRegister(Reg1)); in processInstruction()
1414 MO.setReg(matchRegister(Reg1)); in processInstruction()
1430 MO.setReg(MatchRegisterName(R1)); in processInstruction()
1746 Rss.setReg(matchRegister(Reg1)); in processInstruction()
1772 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1777 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1789 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1794 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1806 Rt.setReg(matchRegister(RegPair)); in processInstruction()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 396 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
435 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
469 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
470 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
|
| D | SparcRegisterInfo.cpp | 193 MI.getOperand(2).setReg(SrcOddReg); in eliminateFrameIndex()
206 MI.getOperand(0).setReg(DestOddReg); in eliminateFrameIndex()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZPostRewrite.cpp | 125 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
132 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
230 SrcMO.setReg(DstReg); in selectMI()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 137 MI->getOperand(Operand + 2).setReg(0); in setDirectAddressInInstr()
139 MI->getOperand(Operand + 4).setReg(0); in setDirectAddressInInstr()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Localizer.cpp | 161 LocalizedMI->getOperand(0).setReg(NewReg); in localizeInterBlock()
169 MOUse.setReg(NewVRegIt->second); in localizeInterBlock()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsOptimizePICCall.cpp | 158 I->getOperand(0).setReg(DstReg); in setCallTargetReg()
249 getCallTargetRegOpnd(*I)->setReg(getReg(Entry)); in visitNode()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 955 MO2.setReg(R600::PRED_SEL_ONE); in reverseBranchCondition()
958 MO2.setReg(R600::PRED_SEL_ZERO); in reverseBranchCondition()
982 .setReg(Pred[2].getReg()); in PredicateInstruction()
984 .setReg(Pred[2].getReg()); in PredicateInstruction()
986 .setReg(Pred[2].getReg()); in PredicateInstruction()
988 .setReg(Pred[2].getReg()); in PredicateInstruction()
996 PMO.setReg(Pred[2].getReg()); in PredicateInstruction()
1352 .setReg(MO.getReg()); in buildSlotOfVectorInstruction()
|
| D | R600ExpandSpecialInstrs.cpp | 103 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
109 Mov->getOperand(MovPredSelIdx).setReg( in runOnMachineFunction()
|
| D | R600EmitClauseMarkers.cpp | 178 Consts[i].first->setReg( in SubstituteKCacheBank()
182 Consts[i].first->setReg( in SubstituteKCacheBank()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXProxyRegErasure.cpp | 114 Op.setReg(To.getReg()); in replaceRegisterUsage()
|