Searched refs:setRegAllocationHint (Results 1 – 5 of 5) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIShrinkInstructions.cpp | 364 MRI.setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg()); in shrinkScalarLogicOp() 365 MRI.setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg()); in shrinkScalarLogicOp() 647 MRI.setRegAllocationHint(Dest->getReg(), 0, Src0->getReg()); in runOnMachineFunction() 648 MRI.setRegAllocationHint(Src0->getReg(), 0, Dest->getReg()); in runOnMachineFunction() 732 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, VCCReg); in runOnMachineFunction() 748 MRI.setRegAllocationHint(SReg, 0, VCCReg); in runOnMachineFunction() 768 MRI.setRegAllocationHint(SDst->getReg(), 0, VCCReg); in runOnMachineFunction() 776 MRI.setRegAllocationHint(Src2->getReg(), 0, VCCReg); in runOnMachineFunction()
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D | SIInstrInfo.cpp | 6207 MRI.setRegAllocationHint(UnusedCarry, 0, RI.getVCC()); in getAddNoCarry()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
D | MachineRegisterInfo.h | 762 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint() function 779 setRegAllocationHint(VReg, /*Type=*/0, PrefReg); in setSimpleHint()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMBaseRegisterInfo.cpp | 370 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in updateRegAllocHint() 372 MRI->setRegAllocationHint(NewReg, in updateRegAllocHint()
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D | ARMLoadStoreOptimizer.cpp | 2369 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps() 2370 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
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