| /third_party/libunwind/src/dwarf/ |
| D | Gparser.c | 55 set_reg (dwarf_state_record_t *sr, unw_word_t regnum, dwarf_where_t where, in set_reg() function
186 set_reg (sr, regnum, DWARF_WHERE_CFAREL, val * dci->data_align); in run_cfi_program()
195 set_reg (sr, regnum, DWARF_WHERE_CFAREL, val * dci->data_align); in run_cfi_program()
204 set_reg (sr, regnum, DWARF_WHERE_CFAREL, val * dci->data_align); in run_cfi_program()
252 set_reg (sr, regnum, DWARF_WHERE_UNDEF, 0); in run_cfi_program()
259 set_reg (sr, regnum, DWARF_WHERE_SAME, 0); in run_cfi_program()
267 set_reg (sr, regnum, DWARF_WHERE_REG, val); in run_cfi_program()
298 set_reg (sr, DWARF_CFA_REG_COLUMN, DWARF_WHERE_REG, regnum); in run_cfi_program()
299 set_reg (sr, DWARF_CFA_OFF_COLUMN, 0, val); /* NOT factored! */ in run_cfi_program()
307 set_reg (sr, DWARF_CFA_REG_COLUMN, DWARF_WHERE_REG, regnum); in run_cfi_program()
[all …]
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| /third_party/libunwind/src/ia64/ |
| D | Gparser.c | 155 set_reg (struct ia64_reg_info *reg, enum ia64_where where, int when, in set_reg() function
299 set_reg (sr->curr.reg + unw.save_order[i], IA64_WHERE_GR, in desc_prologue()
328 set_reg (sr->curr.reg + IA64_REG_B1 + i, IA64_WHERE_GR, in desc_br_gr()
343 set_reg (sr->curr.reg + IA64_REG_B1 + i, IA64_WHERE_SPILL_HOME, in desc_br_mem()
361 set_reg (sr->curr.reg + IA64_REG_R4 + i, IA64_WHERE_SPILL_HOME, in desc_frgr_mem()
372 set_reg (sr->curr.reg + base + i, IA64_WHERE_SPILL_HOME, in desc_frgr_mem()
389 set_reg (sr->curr.reg + IA64_REG_F2 + i, IA64_WHERE_SPILL_HOME, in desc_fr_mem()
406 set_reg (sr->curr.reg + IA64_REG_R4 + i, IA64_WHERE_GR, in desc_gr_gr()
421 set_reg (sr->curr.reg + IA64_REG_R4 + i, IA64_WHERE_SPILL_HOME, in desc_gr_mem()
432 set_reg (sr->curr.reg + IA64_REG_PSP, IA64_WHERE_NONE, in desc_mem_stack_f()
[all …]
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | radeon_uvd.c | 109 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val) in set_reg() function
128 set_reg(dec, dec->reg.data0, addr); in send_cmd()
129 set_reg(dec, dec->reg.data1, addr >> 32); in send_cmd()
132 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off); in send_cmd()
133 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4); in send_cmd()
135 set_reg(dec, dec->reg.cmd, cmd << 1); in send_cmd()
1018 set_reg(dec, dec->reg.cntl, 1); in ruvd_end_frame()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | radeon_uvd.c | 103 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val) in set_reg() function
120 set_reg(dec, dec->reg.data0, addr); in send_cmd()
121 set_reg(dec, dec->reg.data1, addr >> 32); in send_cmd()
124 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off); in send_cmd()
125 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4); in send_cmd()
127 set_reg(dec, dec->reg.cmd, cmd << 1); in send_cmd()
1199 set_reg(dec, dec->reg.cntl, 1); in ruvd_end_frame()
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| D | radeon_vcn_dec.c | 2141 static void set_reg(struct radeon_decoder *dec, unsigned reg, uint32_t val) in set_reg() function
2158 set_reg(dec, dec->reg.data0, addr); in send_cmd()
2159 set_reg(dec, dec->reg.data1, addr >> 32); in send_cmd()
2160 set_reg(dec, dec->reg.cmd, cmd << 1); in send_cmd()
2661 set_reg(dec, dec->reg.cntl, 1); in send_cmd_dec()
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| /third_party/libunwind/scripts/ |
| D | kernel-files.txt | 17 $udir/src/mi/Gset_reg.c $kdir/unwind/set_reg.c
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| /third_party/libunwind/include/ |
| D | libunwind-common.h | 249 #define unw_set_reg UNW_OBJ(set_reg)
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| D | libunwind-common.h.in | 251 #define unw_set_reg UNW_OBJ(set_reg)
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