| /third_party/ltp/tools/sparse/sparse-src/validation/backend/ |
| D | cmp-ops.c | 26 static int setge(int x, int y) in setge() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 94 def : Pat<(setge f32:$lhs, f32:$rhs), (GE_F32 f32:$lhs, f32:$rhs)>;
100 def : Pat<(setge f64:$lhs, f64:$rhs), (GE_F64 f64:$lhs, f64:$rhs)>;
|
| D | WebAssemblyInstrSIMD.td | 508 [setgt, GT_v4f32], [setle, LE_v4f32], [setge, GE_v4f32]] in
513 [setgt, GT_v2f64], [setle, LE_v2f64], [setge, GE_v2f64]] in
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.td | 1450 // bcond-setge
1453 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1460 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1565 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1609 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1752 // setge
1756 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1768 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
|
| D | MipsCondMov.td | 59 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
63 def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
|
| D | MipsInstrInfo.td | 2227 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
3210 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
3214 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
3270 def : MipsPat<(setge RC:$lhs, RC:$rhs),
3278 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
|
| D | MicroMips32r6InstrInfo.td | 1816 def : MipsPat<(brcond (i32 (setge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1822 def : MipsPat<(brcond (i32 (setge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
|
| D | Mips32r6InstrInfo.td | 1036 def : MipsPat<(setge VT:$lhs, VT:$rhs),
|
| D | Mips64InstrInfo.td | 270 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>,
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| D | MicroMipsInstrInfo.td | 987 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatternsHVX.td | 254 defm: MinMax_pats<V6_vminb, V6_vmaxb, vselect, setge, VecQ8, HVI8>;
258 defm: MinMax_pats<V6_vminh, V6_vmaxh, vselect, setge, VecQ16, HVI16>;
262 defm: MinMax_pats<V6_vminw, V6_vmaxw, vselect, setge, VecQ32, HVI32>;
|
| D | HexagonPatterns.td | 580 def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)),
639 def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>;
651 def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>;
682 def: OpmR_RR_pat<Outn<C2_cmpgt>, RevCmp<setge>, i1, I32>;
687 def: OpmR_RR_pat<Outn<C2_cmpgtp>, RevCmp<setge>, i1, I64>;
692 def: OpmR_RR_pat<Outn<A4_vcmpbgt>, RevCmp<setge>, v8i1, V8I8>;
697 def: OpmR_RR_pat<Outn<A2_vcmphgt>, RevCmp<setge>, v4i1, V4I16>;
702 def: OpmR_RR_pat<Outn<A2_vcmpwgt>, RevCmp<setge>, v2i1, V2I32>;
889 defm: SelMinMax16_pats<setge, A2_max, A2_min>;
901 defm: MinMax_pats<A2_min, A2_max, select, setge, i1, I32>;
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 1180 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1208 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1233 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1292 // setge X, 0 is canonicalized to setgt X, -1
|
| /third_party/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 620 #define SETGE(a) CHOICE(setge a, setge a, setge a)
1333 #define SETGE(a) setge a
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.td | 858 def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
882 def : BccPat<setge, BGE>;
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 1306 def setge : PatFrag<(ops node:$lhs, node:$rhs),
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.td | 1727 defm : ISET_FORMAT_SIGNED<setge, CmpGE>;
1865 defm FSetGE : FSET_FORMAT<setge, CmpGE, CmpGE_FTZ>;
|
| /third_party/elfutils/tests/ |
| D | testfile44.expect.bz2 | 1testfile44.o: elf32-elf_i386
2
3Disassembly of section .text:
4
5 0 ... |
| D | testfile45.expect.bz2 | |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.td | 3186 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenAsmMatcher.inc | 2058 Mnemonic = "setge"; // "setnl"
7755 "a\005setae\004setb\005setbe\004sete\004setg\005setge\004setl\005setle\005"
10238 { 7165 /* setge */, X86::SETCCr, Convert__Reg1_0__imm_95_13, AMFBS_None, { MCK_GR8 }, },
10239 { 7165 /* setge */, X86::SETCCm, Convert__Mem85_0__imm_95_13, AMFBS_None, { MCK_Mem8 }, },
24802 { 7165 /* setge */, X86::SETCCr, Convert__Reg1_0__imm_95_13, AMFBS_None, { MCK_GR8 }, },
24803 { 7165 /* setge */, X86::SETCCm, Convert__Mem85_0__imm_95_13, AMFBS_None, { MCK_Mem8 }, },
|