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Searched refs:sh_base_reg (Results 1 – 1 of 1) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_draw.cpp1549 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX]; in si_emit_draw_packets() local
1585 radeon_emit((sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); in si_emit_draw_packets()
1586 radeon_emit((sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); in si_emit_draw_packets()
1603 radeon_emit((sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); in si_emit_draw_packets()
1604 radeon_emit((sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); in si_emit_draw_packets()
1605 radeon_emit(((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) | in si_emit_draw_packets()
1635 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4, sctx->num_vs_blit_sgprs); in si_emit_draw_packets()
1645 sh_base_reg != sctx->last_sh_base_reg) { in si_emit_draw_packets()
1647 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3); in si_emit_draw_packets()
1655 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2); in si_emit_draw_packets()
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