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Searched refs:si_get_vs_inline (Results 1 – 2 of 2) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_draw.cpp114 struct si_shader *old_vs = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current; in si_update_shaders()
238 key.index |= si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ctx_reg.ngg.vgt_stages.index; in si_update_shaders()
244 key.u.vs_wave32 = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->wave_size == 32; in si_update_shaders()
254 si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->pa_cl_vs_out_cntl) in si_update_shaders()
1187 struct si_shader *hw_vs = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current; in si_emit_rasterizer_prim_state()
1320 … G_03096C_PRIM_GRP_SIZE_GFX11(si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ge_cntl); in gfx10_emit_ge_cntl()
1323 … S_03096C_VERTS_PER_SUBGRP(si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ngg.hw_max_esverts) | in gfx10_emit_ge_cntl()
1332 ge_cntl = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ge_cntl; in gfx10_emit_ge_cntl()
2417 struct si_shader_selector *hw_vs = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->cso; in si_draw()
2462 … sctx->ngg_culling = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->key.ge.opt.ngg_culling; in si_draw()
Dsi_pipe.h1740 si_get_vs_inline(struct si_context *sctx, enum si_has_tess has_tess, enum si_has_gs has_gs) in si_get_vs_inline() function
1752 return si_get_vs_inline(sctx, sctx->shader.tes.cso ? TESS_ON : TESS_OFF, in si_get_vs()