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Searched refs:sltiu (Results 1 – 13 of 13) sorted by relevance

/third_party/elfutils/tests/
Dtestfile-riscv64-dis1.expect.bz2 ... sp,3 70 104: 13 30 00 00 sltiu zero,zero,0 71 108: 93 30 ...
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrInfo.td439 // op2 can be cmpi or slti/sltiu
659 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
686 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
1082 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
1137 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1187 def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIM16Alu> {
1197 def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIM16Alu> {
1205 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
DMipsSchedule.td329 def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu
DMipsScheduleP5600.td39 // and, lui, nor, or, slti, sltiu, sub, subu, xor
DMips64InstrInfo.td130 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
DMicroMipsInstrInfo.td728 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
DMipsScheduleGeneric.td45 // rotr, rotrv, seb, seh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl,
DMipsInstrInfo.td1218 // e.g. addiu, sltiu
2040 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.h267 void sltiu(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
DIceInstMIPS32.cpp1036 Asm->sltiu(getDest(), getSrc(0), Imm); in emitIAS()
DIceAssemblerMIPS32.cpp1014 void AssemblerMIPS32::sltiu(const Operand *OpRt, const Operand *OpRs, in sltiu() function in Ice::MIPS32::AssemblerMIPS32
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td413 def SLTIU : ALU_ri<0b011, "sltiu">;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc5088 "slli.h\006slli.w\004sllv\003slt\004slti\005sltiu\004sltu\003sne\004snei"
7732 …{ 8464 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU…
7733 …{ 8464 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdE…
7734 …{ 8464 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMi…
7735 …{ 8464 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU1…
11238 { 8464 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11239 { 8464 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },