Searched refs:sltu (Results 1 – 14 of 14) sorted by relevance
460 // op2 can be cmp or slt/sltu655 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;682 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;1074 def SelTBteqZSltu: SelT<"bteqz", "sltu">;1129 def SelTBtneZSltu: SelT<"btnez", "sltu">;1222 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIM16Alu>{1226 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {1232 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
155 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>, GPR_64;1219 "sltu\t$rs, $rt, $imm">, GPR_64;1220 def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
758 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,1408 defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>, ISA_MICROMIPS;
330 def II_SLT_SLTU : InstrItinClass; // slt and sltu
221 // add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu,
45 // rotr, rotrv, seb, seh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl,
2063 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>,2760 defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>, ISA_MIPS1, GPR_32;
269 void sltu(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
1041 Asm->sltu(getDest(), getSrc(0), getSrc(1)); in emitIAS()
1008 void AssemblerMIPS32::sltu(const Operand *OpRd, const Operand *OpRs, in sltu() function in Ice::MIPS32::AssemblerMIPS32
... ra,a6 103 188: 33 30 04 00 sltu zero,s0,zero 104 18c: b3 ...
430 def SLTU : ALU_rr<0b0000000, 0b011, "sltu">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;604 // sgt/sgtu are recognised by the GNU assembler but the canonical slt/sltu738 def : InstAlias<"sltu $rd, $rs1, $imm12",
5088 "slli.h\006slli.w\004sllv\003slt\004slti\005sltiu\004sltu\003sne\004snei"7736 …{ 8470 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs,…7737 …{ 8470 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_…7738 …{ 8470 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMF…7739 …{ 8470 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64b…7740 …{ 8470 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasS…7741 …{ 8470 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_I…7742 …{ 8470 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_…7743 …{ 8470 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMF…7744 …{ 8470 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64b…[all …]
8896 /* 104 */ "sltu $\x01, $\x03\0"