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Searched refs:srcin (Results 1 – 21 of 21) sorted by relevance

/third_party/optimized-routines/string/aarch64/
Dstrcpy-mte.S17 #define srcin x1 macro
60 bic src, srcin, 15
65 lsl shift, srcin, 2
82 sub tmp, src, srcin
87 ldr dataq, [srcin]
88 ldr dataq2, [srcin, tmp]
104 ldr data1, [srcin]
105 ldr data2, [srcin, tmp]
115 ldr dataw1, [srcin]
116 ldr dataw2, [srcin, tmp]
[all …]
Dstrlen.S16 #define srcin x0 macro
78 and tmp1, srcin, MIN_PAGE_SIZE - 1
83 ldp data1, data2, [srcin]
116 ldp data1, data2, [srcin, 16]
142 bic src, srcin, 31
155 sub len, src, srcin
179 bic src, srcin, 31
191 lsl shift, srcin, 1
Dmemchr-mte.S16 #define srcin x0 macro
49 bic src, srcin, 15
56 lsl shift, srcin, 2
65 add result, srcin, synd, lsr 2
71 sub tmp, src, srcin
100 add tmp, srcin, cntin
Dstrnlen.S16 #define srcin x0 macro
47 bic src, srcin, 15
53 lsl shift, srcin, 2
68 sub tmp, src, srcin
97 sub result, src, srcin
Dstrlen-mte.S16 #define srcin x0 macro
43 bic src, srcin, 15
48 lsl shift, srcin, 2
70 sub result, src, srcin
Dstrchrnul-mte.S16 #define srcin x0 macro
45 bic src, srcin, 15
52 lsl tmp2, srcin, 2
61 add result, srcin, tmp1, lsr 2
Dstrchr-mte.S16 #define srcin x0 macro
47 bic src, srcin, 15
59 lsl tmp3, srcin, 2
71 add result, srcin, tmp1, lsr 2
Dstrcpy.S23 #define srcin x1 macro
95 and tmp2, srcin, #(MIN_PAGE_SIZE - 1)
97 and to_align, srcin, #15
107 ldp data1, data2, [srcin]
197 sub src, srcin, to_align
250 bic src, srcin, #15
Dstrrchr-mte.S16 #define srcin x0 macro
48 bic src, srcin, 15
52 tst srcin, 15
63 lsl shift, srcin, 2
Dstrchrnul.S17 #define srcin x0 macro
56 bic src, srcin, #31 /* Work with aligned 32-byte hunks. */
58 ands tmp1, srcin, #31
Dmemrchr.S16 #define srcin x0 macro
50 add end, srcin, cntin
108 cmp tmp, srcin
Dstrchr.S17 #define srcin x0 macro
61 bic src, srcin, #31 /* Work with aligned 32-byte hunks. */
63 ands tmp1, srcin, #31
Dmemchr.S17 #define srcin x0 macro
62 bic src, srcin, #31
64 ands soff, srcin, #31
Dstrrchr.S17 #define srcin x0 macro
65 bic src, srcin, #31 /* Work with aligned 32-byte hunks. */
68 ands tmp1, srcin, #31
/third_party/optimized-routines/string/arm/
Dstrlen-armv6t2.S31 #define srcin r0 macro
44 pld [srcin, #0]
46 bic src, srcin, #7
48 ands tmp1, srcin, #7 /* (8 - bytes) to alignment. */
/third_party/flutter/skia/src/core/
DSkBlendMode.cpp93 case SkBlendMode::kSrcIn: stage = SkRasterPipeline::srcin; break; in SkBlendMode_AppendStages()
DSkRasterPipeline.h68 M(srcatop) M(srcin) M(srcout) M(srcover) \
/third_party/skia/src/core/
DSkBlendMode.cpp95 case SkBlendMode::kSrcIn: stage = SkRasterPipeline::srcin; break; in SkBlendMode_AppendStages()
DSkRasterPipeline.h71 M(srcatop) M(srcin) M(srcout) M(srcover) \
/third_party/flutter/skia/src/opts/
DSkRasterPipeline_opts.h1388 BLEND_MODE(srcin) { return s * da; } in BLEND_MODE() argument
3239 BLEND_MODE(srcin) { return div255( s*da ); }
/third_party/skia/src/opts/
DSkRasterPipeline_opts.h1410 BLEND_MODE(srcin) { return s * da; } in BLEND_MODE() argument
3409 BLEND_MODE(srcin) { return div255( s*da ); }