Searched refs:stencil_write_mask (Results 1 – 21 of 21) sorted by relevance
32 dEQP-VKSC.dynamic_state.compute_transfer.single.compute.stencil_write_mask.before33 dEQP-VKSC.dynamic_state.compute_transfer.single.compute.stencil_write_mask.after82 dEQP-VKSC.dynamic_state.compute_transfer.single.transfer.stencil_write_mask.before83 dEQP-VKSC.dynamic_state.compute_transfer.single.transfer.stencil_write_mask.after
160 state->dynamic.stencil_write_mask.front = cmd_buffer->state.dynamic.stencil_write_mask.front; in radv_meta_save()161 state->dynamic.stencil_write_mask.back = cmd_buffer->state.dynamic.stencil_write_mask.back; in radv_meta_save()290 cmd_buffer->state.dynamic.stencil_write_mask.front = state->dynamic.stencil_write_mask.front; in radv_meta_restore()291 cmd_buffer->state.dynamic.stencil_write_mask.back = state->dynamic.stencil_write_mask.back; in radv_meta_restore()
93 .stencil_write_mask =198 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask, in radv_bind_dynamic_state()199 sizeof(src->stencil_write_mask))) { in radv_bind_dynamic_state()200 dest->stencil_write_mask = src->stencil_write_mask; in radv_bind_dynamic_state()1727 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) | in radv_emit_stencil()1731 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) | in radv_emit_stencil()5754 state->dynamic.stencil_write_mask.front = writeMask; in radv_CmdSetStencilWriteMask()5756 state->dynamic.stencil_write_mask.back = writeMask; in radv_CmdSetStencilWriteMask()
1270 } stencil_write_mask; member
2049 dynamic->stencil_write_mask.front = info->ds.front.write_mask; in radv_pipeline_init_dynamic_state()2050 dynamic->stencil_write_mask.back = info->ds.back.write_mask; in radv_pipeline_init_dynamic_state()
17 dEQP-VK.dynamic_state.compute_transfer.single.compute.stencil_write_mask.before18 dEQP-VK.dynamic_state.compute_transfer.single.compute.stencil_write_mask.after77 dEQP-VK.dynamic_state.compute_transfer.single.transfer.stencil_write_mask.before78 dEQP-VK.dynamic_state.compute_transfer.single.transfer.stencil_write_mask.after
32 dEQP-VK.dynamic_state.compute_transfer.single.compute.stencil_write_mask.before33 dEQP-VK.dynamic_state.compute_transfer.single.compute.stencil_write_mask.after92 dEQP-VK.dynamic_state.compute_transfer.single.transfer.stencil_write_mask.before93 dEQP-VK.dynamic_state.compute_transfer.single.transfer.stencil_write_mask.after
21 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.before22 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.after81 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.before82 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.after
67 dEQP-VKSC.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.before68 dEQP-VKSC.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.after117 dEQP-VKSC.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.before118 dEQP-VKSC.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.after
113 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.before114 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.after173 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.before174 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.after
1791 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask, in cmd_buffer_bind_pipeline_static_state()1792 sizeof(src->stencil_write_mask))) { in cmd_buffer_bind_pipeline_static_state()1793 dest->stencil_write_mask = src->stencil_write_mask; in cmd_buffer_bind_pipeline_static_state()2965 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask & 0xff; in v3dv_CmdSetStencilWriteMask()2967 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask & 0xff; in v3dv_CmdSetStencilWriteMask()
296 config.stencil_write_mask = write_mask; in pack_single_stencil_cfg()
1119 config.stencil_write_mask = in v3dX()1120 i == 0 ? dynamic_state->stencil_write_mask.front : in v3dX()1121 dynamic_state->stencil_write_mask.back; in v3dX()
2675 dynamic->stencil_write_mask.front = ~0; in pipeline_init_dynamic_state()2676 dynamic->stencil_write_mask.back = ~0; in pipeline_init_dynamic_state()2722 dynamic->stencil_write_mask.front = pDepthStencilState->front.writeMask; in pipeline_init_dynamic_state()2723 dynamic->stencil_write_mask.back = pDepthStencilState->back.writeMask; in pipeline_init_dynamic_state()
928 } stencil_write_mask; member
230 config.stencil_write_mask = front->writemask; in v3d_create_depth_stencil_alpha_state()249 config.stencil_write_mask = back->writemask; in v3d_create_depth_stencil_alpha_state()
195 cfg.stencil_write_mask = st.writemask; in agx_pack_rasterizer_face()204 cfg.stencil_write_mask = 0xFF; in agx_pack_rasterizer_face()