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Searched refs:tcs_in_out_eq (Results 1 – 12 of 12) sorted by relevance

/third_party/mesa3d/src/amd/common/
Dac_nir_lower_tess_io_to_mem.c132 bool tcs_in_out_eq; member
265 if (!st->tcs_in_out_eq) in lower_ls_output_store()
283 if (!st->tcs_in_out_eq) in filter_load_tcs_per_vertex_input()
675 bool tcs_in_out_eq, in ac_nir_lower_ls_outputs_to_mem() argument
681 .tcs_in_out_eq = tcs_in_out_eq, in ac_nir_lower_ls_outputs_to_mem()
682 .tcs_temp_only_inputs = tcs_in_out_eq ? tcs_temp_only_inputs : 0, in ac_nir_lower_ls_outputs_to_mem()
695 bool tcs_in_out_eq) in ac_nir_lower_hs_inputs_to_mem() argument
700 .tcs_in_out_eq = tcs_in_out_eq, in ac_nir_lower_hs_inputs_to_mem()
Dac_nir.h75 bool tcs_in_out_eq,
81 bool tcs_in_out_eq);
/third_party/mesa3d/src/amd/compiler/
Daco_instruction_selection.h107 bool tcs_in_out_eq = false; member
Daco_shader_info.h114 bool tcs_in_out_eq; member
Daco_instruction_selection_setup.cpp304 ctx->tcs_in_out_eq = ctx->program->info.vs.tcs_in_out_eq; in setup_tcs_info()
Daco_instruction_selection.cpp5218 if (ctx->shader->info.stage != MESA_SHADER_TESS_CTRL || !ctx->tcs_in_out_eq) in load_input_from_temps()
11950 ctx.tcs_in_out_eq ? i == 0 : (shader_count >= 2 && !empty_shader && !(ngg_gs && i == 1)); in select_program()
11952 ctx.tcs_in_out_eq ? i == 1 : (check_merged_wave_info && !(ngg_gs && i == 1)); in select_program()
12019 if (i == 0 && ctx.stage == vertex_tess_control_hs && ctx.tcs_in_out_eq) { in select_program()
/third_party/mesa3d/src/amd/vulkan/
Dradv_aco_shader_info.h82 ASSIGN_FIELD(vs.tcs_in_out_eq); in radv_aco_convert_shader_info()
Dradv_shader.h270 bool tcs_in_out_eq; member
Dradv_shader.c1167 NIR_PASS_V(nir, ac_nir_lower_ls_outputs_to_mem, NULL, info->vs.tcs_in_out_eq, in radv_lower_io_to_mem()
1177 NIR_PASS_V(nir, ac_nir_lower_hs_inputs_to_mem, NULL, info->vs.tcs_in_out_eq); in radv_lower_io_to_mem()
Dradv_pipeline.c3849 stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq = in gather_tess_info()
3855 if (stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq) in gather_tess_info()
3864 …stages[MESA_SHADER_TESS_CTRL].info.vs.tcs_in_out_eq = stages[MESA_SHADER_VERTEX].info.vs.tcs_in_ou… in gather_tess_info()
/third_party/mesa3d/docs/relnotes/
D20.2.0.rst3892 - aco: set tcs_in_out_eq=false if float controls of VS and TCS stages differ
D21.1.0.rst5388 - radv: Determine tcs_in_out_eq in radv_pipeline instead of the compiler.