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Searched refs:v1i64 (Results 1 – 25 of 32) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
185 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
211 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
233 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
DARMInstrNEON.td1096 def : Pat<(insert_subvector undef, (v1i64 DPR:$src), (i32 0)),
3545 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3547 v1i64, v1i64, OpNode, Commutable>;
3653 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3655 v1i64, v1i64, IntOp, Commutable>;
3667 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3669 v1i64, v1i64, IntOp>;
3977 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
4000 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
4031 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
[all …]
DARMTargetTransformInfo.cpp687 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
688 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
689 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
690 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
DARMScheduleA57.td1127 "VSLI(v8i8|v4i16|v2i32|v1i64)", "VSRI(v8i8|v4i16|v2i32|v1i64)")>;
1135 "VSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;
1144 "VQRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)", "VQSHL(s|u)(v8i8|v4i16|v2i32|v1i64)",
1145 "VRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;
1220 "VMOV(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v1i64|v2i64|v2f32|v4f32)",
DARMRegisterInfo.td404 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
425 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
432 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
DARMScheduleR52.td775 (instregex "(VADD|VSUB)(v8i8|v4i16|v2i32|v1i64)")>;
819 def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VQABS(v8i8|v4i16|v2i32|v1i64)")>;
822 (instregex "(VQADD|VQSUB)(u|s)(v8i8|v4i16|v2i32|v1i64)")>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp3200 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3227 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3254 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3281 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3308 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3335 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3362 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3389 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3416 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3436 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
[all …]
DAArch64SchedFalkorDetails.td591 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64|v2i32)rz$")>;
598 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v1i32|v1i64|v2f32)$")>;
658 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^ADD(v1i64|v2i32|v4i16|v8i8)$")>;
662 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^NEG(v1i64|v2i32|v4i16|v8i8)$")>;
663 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^SUB(v1i64|v2i32|v4i16|v8i8)$")>;
669 …XVY_2cyc], (instregex "^((S|U)?(MAX|MIN)P?|ABS|ADDP|CM(EQ|GE|HS|GT|HI))(v1i64|v2i32|v4i16|v8i8)$…
670 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|GE|HS|GT|HI)(v1i64|v2i32|v4i16|v8i8)$")>;
671 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|LE|GE|GT|LT)(v1i64|v2i32|v4i16|v8i8)rz$")>;
672 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CMTST(v1i64|v2i32|v4i16|v8i8)$")>;
681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
[all …]
DAArch64SchedA57.td347 // D form - v1i8, v1i16, v1i32, v1i64
374 …e_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>;
392 def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>;
410 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
423 // D form - v1i32, v1i64
438 …yc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
445 …InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
476 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
485 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
500 // D form - v1i8, v1i16, v1i32, v1i64
[all …]
DAArch64CallingConvention.td109 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
118 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
151 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
226 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
242 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
263 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
285 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
347 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
DAArch64InstrInfo.td2109 def : Pat <(v1i64 (scalar_to_vector (i64
2114 def : Pat <(v1i64 (scalar_to_vector (i64
2141 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
2263 def : Pat <(v1i64 (scalar_to_vector (i64
2287 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
2471 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2803 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
2879 def : Pat<(store (v1i64 FPR64:$Rt),
3018 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
3162 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
[all …]
DAArch64SchedKryoDetails.td147 (instregex "(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>;
213 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>;
231 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
261 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>;
285 (instregex "(S|U)SHL(d|v8i8|v4i16|v2i32|v1i64)$")>;
375 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;
513 (instregex "CM(EQ|GE|HS|GT|HI|TST)(v8i8|v4i16|v2i32|v1i64)$")>;
525 (instregex "CM(EQ|LE|GE|GT|LT)(v8i8|v4i16|v2i32|v1i64)rz$")>;
693 (instregex "FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64)rz")>;
735 (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v1i32|v1i64|v2f32)$")>;
[all …]
DAArch64InstrFormats.td5353 def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)),
5384 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
5385 (v1i64 V64:$RHS))),
5577 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
5603 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
6156 def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
6546 def v1i64 : BaseSIMDThreeScalar<U, 0b111, opc, FPR64, asm,
6547 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
6552 def v1i64 : BaseSIMDThreeScalar<U, 0b111, opc, FPR64, asm,
6553 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
[all …]
DAArch64SchedThunderX2T99.td1274 def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^PMULL(v1i64|v2i64)")>;
1306 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1335 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
1342 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;
1421 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
1458 (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
1468 (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
DAArch64ISelLowering.cpp153 addDRTypeForNEON(MVT::v1i64); in AArch64TargetLowering()
731 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand); in AArch64TargetLowering()
732 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand); in AArch64TargetLowering()
733 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
734 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
737 setOperationAction(ISD::MUL, MVT::v1i64, Expand); in AArch64TargetLowering()
770 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand); in AArch64TargetLowering()
927 if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64) in addTypeForNEON()
2955 SDValue Result = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, in LowerINTRINSIC_WO_CHAIN()
2957 Result = DAG.getNode(ISD::ABS, dl, MVT::v1i64, Result); in LowerINTRINSIC_WO_CHAIN()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h107 v1i64 = 57, // 1 x i64 enumerator
344 SimpleTy == MVT::v1i64 || SimpleTy == MVT::v4f16 || in is64BitVector()
495 case v1i64: in getVectorElementType()
656 case v1i64: in getVectorNumElements()
741 case v1i64: in getSizeInBits()
974 if (NumElements == 1) return MVT::v1i64; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenCallingConv.inc63 if (LocVT == MVT::v1i64 ||
233 if (LocVT == MVT::v1i64 ||
352 if (LocVT == MVT::v1i64 ||
419 if (LocVT == MVT::v1i64 ||
513 if (LocVT == MVT::v1i64 ||
601 if (LocVT == MVT::v1i64 ||
704 if (LocVT == MVT::v1i64 ||
818 if (LocVT == MVT::v1i64 ||
875 if (LocVT == MVT::v1i64 ||
DARMGenDAGISel.inc1227 /* 2603*/ /*SwitchType*/ 19, MVT::v1i64,// ->2624
1232 MVT::v1i64, 5/*#Ops*/, 1, 0, 2, 3, 4,
1233 …v1i64] } (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vd), (and:{ *:[v1i64] } DPR:…
1234 … // Dst: (VBSLd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vd, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
1643 /* 3404*/ OPC_CheckType, MVT::v1i64,
1648 MVT::v1i64, 5/*#Ops*/, 1, 0, 2, 3, 4,
1649 …v1i64] } (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vd), (and:{ *:[v1i64] } DPR:…
1650 … // Dst: (VBSLd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vd, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
1670 /* 3456*/ OPC_CheckType, MVT::v1i64,
1675 MVT::v1i64, 5/*#Ops*/, 1, 0, 2, 3, 4,
[all …]
DARMGenFastISel.inc892 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(Op0, Op0IsKill);
1011 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(Op0, Op0IsKill);
1118 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(Op0, Op0IsKill);
1332 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1i64_r(Op0, Op0IsKill);
1439 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(Op0, Op0IsKill);
1578 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v1i64_r(RetVT, Op0, Op0IsKill);
3274 if (RetVT.SimpleTy != MVT::v1i64)
3299 case MVT::v1i64: return fastEmit_ARMISD_VSHLs_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3371 if (RetVT.SimpleTy != MVT::v1i64)
3396 case MVT::v1i64: return fastEmit_ARMISD_VSHLu_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
[all …]
DARMGenGlobalISel.inc1621 …// (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } …
3737 …// (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } …
7902 … *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (REG_SEQUENCE:{ *:[v2i64] } QPR:{ *:[i32] }, DPR:{ *…
8069 // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src
8083 // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src
8167 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src
8181 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src
8195 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src
8209 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src
8223 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc305 if (LocVT == MVT::v1i64 ||
361 LocVT == MVT::v1i64 ||
549 if (LocVT == MVT::v1i64 ||
622 LocVT == MVT::v1i64 ||
704 LocVT == MVT::v1i64 ||
786 LocVT == MVT::v1i64 ||
823 if (LocVT == MVT::v1i64 ||
1118 if (LocVT == MVT::v1i64 ||
DAArch64GenFastISel.inc191 if (RetVT.SimpleTy != MVT::v1i64)
216 case MVT::v1i64: return fastEmit_AArch64ISD_CMEQz_MVT_v1i64_r(RetVT, Op0, Op0IsKill);
279 if (RetVT.SimpleTy != MVT::v1i64)
304 case MVT::v1i64: return fastEmit_AArch64ISD_CMGEz_MVT_v1i64_r(RetVT, Op0, Op0IsKill);
367 if (RetVT.SimpleTy != MVT::v1i64)
392 case MVT::v1i64: return fastEmit_AArch64ISD_CMGTz_MVT_v1i64_r(RetVT, Op0, Op0IsKill);
455 if (RetVT.SimpleTy != MVT::v1i64)
480 case MVT::v1i64: return fastEmit_AArch64ISD_CMLEz_MVT_v1i64_r(RetVT, Op0, Op0IsKill);
543 if (RetVT.SimpleTy != MVT::v1i64)
568 case MVT::v1i64: return fastEmit_AArch64ISD_CMLTz_MVT_v1i64_r(RetVT, Op0, Op0IsKill);
[all …]
DAArch64GenGlobalISel.inc1790 …v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 371:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i6…
1811 …v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 429:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i6…
1832 …v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 371:{ *:[iPTR] }, V64:{ *:[v2i32…
1853 …v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 429:{ *:[iPTR] }, V64:{ *:[v2i32…
1878 …/ (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (ADDv1i64:{ *:[v1i64] …
4363 …/ (sub:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SUBv1i64:{ *:[v1i64] …
5802 …// (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (ANDv8i8:{ *:[v1i64] } …
6219 …// (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (ORRv8i8:{ *:[v1i64] } V…
6864 …// (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (EORv8i8:{ *:[v1i64] } …
6998 …[v2i64] } V64:{ *:[v1i64] }:$Rn, (undef:{ *:[v1i64] })) => (INSERT_SUBREG:{ *:[v2i64] } (IMPLICI…
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp202 case MVT::v1i64: return VectorType::get(Type::getInt64Ty(Context), 1); in getTypeForEVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td82 def v1i64 : ValueType<64 , 57>; // 1 x i64 vector value

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