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Searched refs:v32i1 (Results 1 – 18 of 18) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td172 def maskzeroupperv32i1 : maskzeroupper<v32i1, VK32>;
178 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
181 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
184 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
236 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
239 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
296 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
304 (v32i1 VK32:$mask), (iPTR 0))),
309 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
321 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
[all …]
DX86CallingConv.td84 // Promote v8i1/v16i1/v32i1 arguments to i32.
85 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,
161 // Promote v32i1 arguments to i32.
162 CCIfType<[v32i1], CCPromoteToType<i32>>,
230 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
538 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
823 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
DX86TargetTransformInfo.cpp1289 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, in getCastInstrCost()
1290 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, in getCastInstrCost()
1297 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, in getCastInstrCost()
1298 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, in getCastInstrCost()
2701 { ISD::AND, MVT::v32i1, 11 }, in getArithmeticReductionCost()
2707 { ISD::OR, MVT::v32i1, 11 }, in getArithmeticReductionCost()
DX86RegisterInfo.td601 def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
619 def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
DX86ISelLowering.cpp1204 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom); in X86TargetLowering()
1729 addRegisterClass(MVT::v32i1, &X86::VK32RegClass); in X86TargetLowering()
1732 for (auto VT : { MVT::v32i1, MVT::v64i1 }) { in X86TargetLowering()
1751 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom); in X86TargetLowering()
1753 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom); in X86TargetLowering()
1755 for (auto VT : { MVT::v16i1, MVT::v32i1 }) in X86TargetLowering()
2078 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI()) in getPreferredVectorAction()
2092 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI()) in getRegisterTypeForCallingConv()
2104 return MVT::v32i1; in getRegisterTypeForCallingConv()
2116 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI()) in getNumRegistersForCallingConv()
[all …]
DX86InstrAVX512.td169 def v32i1_info : X86KVectorVTInfo<VK32, VK32WM, v32i1>;
2841 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2880 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))),
2882 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))),
2934 defm : operation_gpr_mask_copy_lowering<VK32, v32i1>;
3310 defm D : avx512_mask_setop<VK32, v32i1, Val>;
3342 defm : operation_subvector_mask_lowering<VK1, v1i1, VK32, v32i1>;
3348 defm : operation_subvector_mask_lowering<VK2, v2i1, VK32, v32i1>;
3353 defm : operation_subvector_mask_lowering<VK4, v4i1, VK32, v32i1>;
3357 defm : operation_subvector_mask_lowering<VK8, v8i1, VK32, v32i1>;
[all …]
DX86ISelDAGToDAG.cpp4287 case MVT::v32i1: return X86::VK32RegClassID; in tryVPTESTM()
DX86InstrCompiler.td592 defm _VK32 : CMOVrr_PSEUDO<VK32, v32i1>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h65 v32i1 = 19, // 32 x i1 enumerator
335 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 || in is32BitVector()
433 case v32i1: in getVectorElementType()
573 case v32i1: in getVectorNumElements()
720 case v32i1: in getSizeInBits()
928 if (NumElements == 32) return MVT::v32i1; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td304 [v32i1, v64i1, v32i1]>;
306 [v16i1, v32i1, v16i1]>;
DHexagonISelLoweringHVX.cpp40 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
50 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc521 if (LocVT == MVT::v32i1) {
822 LocVT == MVT::v32i1) {
1519 if (LocVT == MVT::v32i1) {
1888 LocVT == MVT::v32i1) {
2359 LocVT == MVT::v32i1) {
2766 if (LocVT == MVT::v32i1) {
3047 if (LocVT == MVT::v32i1) {
3617 if (LocVT == MVT::v32i1) {
3831 if (LocVT == MVT::v32i1) {
DX86GenGlobalISel.inc3911 … (and:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KANDDrr:{ *:[v32i1] …
5485 …// (or:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KORDrr:{ *:[v32i1] …
6807 … (xor:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KXORDrr:{ *:[v32i1] …
6935 …// (concat_vectors:{ *:[v32i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) => (KUNPCKW…
6954 …v64i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KUNPCKDQrr:{ *:[v64i1] } VK32:{…
7048 …// (bitconvert:{ *:[i32] } VK32:{ *:[v32i1] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } VK32:{ *:[v…
7058 … (bitconvert:{ *:[f32] } VK32:{ *:[v32i1] }:$src) => (VMOVDI2SSZrr:{ *:[f32] } (KMOVDrk:{ *:[i32…
7231 …// (bitconvert:{ *:[v32i1] } GR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v32i1] } GR32:{ *:…
7239 …// (bitconvert:{ *:[v32i1] } FR32X:{ *:[f32] }:$src) => (KMOVDkr:{ *:[v32i1] } (VMOVSS2DIZrr:{ *…
10623 …// (anyext:{ *:[v32i8] } VK32:{ *:[v32i1] }:$src) => (VPMOVM2BZ256rr:{ *:[v32i8] } VK32:{ *:[v32…
[all …]
DX86GenFastISel.inc332 case MVT::v32i1: return fastEmit_ISD_ANY_EXTEND_MVT_v32i1_r(RetVT, Op0, Op0IsKill);
1548 case MVT::v32i1: return fastEmit_ISD_SIGN_EXTEND_MVT_v32i1_r(RetVT, Op0, Op0IsKill);
7193 if (RetVT.SimpleTy != MVT::v32i1)
7374 case MVT::v32i1: return fastEmit_ISD_AND_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
8200 if (RetVT.SimpleTy != MVT::v32i1)
8381 case MVT::v32i1: return fastEmit_ISD_OR_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
10350 if (RetVT.SimpleTy != MVT::v32i1)
10531 case MVT::v32i1: return fastEmit_ISD_XOR_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
12364 if (RetVT.SimpleTy != MVT::v32i1)
12385 case MVT::v32i1: return fastEmit_X86ISD_KADD_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
[all …]
DX86GenRegisterInfo.inc4489 /* 34 */ MVT::v32i1, MVT::Other,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp164 case MVT::v32i1: return VectorType::get(Type::getInt1Ty(Context), 32); in getTypeForEVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td40 def v32i1 : ValueType<32 , 19>; // 32 x i1 vector value
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsics.td233 def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1