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Searched refs:v32i16 (Results 1 – 25 of 28) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td85 CCIfType<[v16i32,v32i16,v64i8],
91 CCIfType<[v16i32,v32i16,v64i8],
117 CCIfType<[v16i32,v32i16,v64i8],
DHexagonIntrinsics.td284 def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))),
285 (v512i1 (V6_vandvrt (v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
296 def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))),
297 (v32i16 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
DHexagonIntrinsicsV60.td31 def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))),
32 (v512i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
40 def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))),
41 (v32i16 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
DHexagonRegisterInfo.td290 [v32i16, v64i16, v32i16]>;
DHexagonISelLoweringHVX.cpp16 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
26 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
198 for (MVT T: {MVT::v32i8, MVT::v32i16, MVT::v16i8, MVT::v16i16, MVT::v16i32}) in initializeHVXLowering()
201 for (MVT T: {MVT::v64i8, MVT::v64i16, MVT::v32i8, MVT::v32i16, MVT::v32i32}) in initializeHVXLowering()
DHexagonISelDAGToDAG.cpp109 case MVT::v32i16: in SelectIndexedLoad()
499 case MVT::v32i16: in SelectIndexedStore()
DHexagonPatternsHVX.td363 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i16)),
DHexagonInstrInfo.cpp2661 case MVT::v32i16: in isValidAutoIncImm()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h88 v32i16 = 40, // 32 x i16 enumerator
369 SimpleTy == MVT::v64i8 || SimpleTy == MVT::v32i16 || in is512BitVector()
466 case v32i16: in getVectorElementType()
575 case v32i16: in getVectorNumElements()
792 case v32i16: in getSizeInBits()
953 if (NumElements == 32) return MVT::v32i16; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp354 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
355 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
356 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
357 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
506 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw in getArithmeticInstrCost()
507 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
508 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw in getArithmeticInstrCost()
1006 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw in getShuffleCost()
1009 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw in getShuffleCost()
1013 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw in getShuffleCost()
[all …]
DX86InstrVecCompiler.td86 defm : subvector_subreg_lowering<VR128, v8i16, VR512, v32i16, sub_xmm>;
97 defm : subvector_subreg_lowering<VR256, v16i16, VR512, v32i16, sub_ymm>;
135 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i16, v8i16, v16i32, sub_xmm>;
142 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v32i16, v16i16, v16i32, sub_ymm>;
151 defm : subvec_zero_lowering<"DQA", VR128, v32i16, v8i16, v16i32, sub_xmm>;
158 defm : subvec_zero_lowering<"DQAY", VR256, v32i16, v16i16, v16i32, sub_ymm>;
DX86CallingConv.td120 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
150 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
557 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
577 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
624 CCIfType<[v64i8, v32i16, v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
689 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
747 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
764 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
DX86InstrFragmentsSIMD.td812 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
873 (v32i16 (alignedload node:$ptr))>;
999 def bc_v32i16 : PatFrag<(ops node:$in), (v32i16 (bitconvert node:$in))>;
DX86RegisterInfo.td577 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
581 def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
DX86InstrAVX512.td418 def : Pat<(v32i16 immAllZerosV), (AVX512_512_SET0)>;
936 def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))),
938 (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
965 def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))),
967 (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
1447 def : Pat<(v32i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))),
1449 def : Pat<(v32i16 (X86VBroadcast
1452 def : Pat<(v32i16 (X86VBroadcast
1457 def : Pat<(v32i16 (X86VBroadcast (loadi16 addr:$src))),
1483 def : Pat<(v32i16 (X86SubVBroadcast (loadv16i16 addr:$src))),
[all …]
DX86ISelLowering.cpp1628 setOperationAction(ISD::BITCAST, MVT::v32i16, Custom); in X86TargetLowering()
1768 addRegisterClass(MVT::v32i16, &X86::VR512RegClass); in X86TargetLowering()
1776 setOperationAction(ISD::MUL, MVT::v32i16, Legal); in X86TargetLowering()
1778 setOperationAction(ISD::MULHS, MVT::v32i16, Legal); in X86TargetLowering()
1779 setOperationAction(ISD::MULHU, MVT::v32i16, Legal); in X86TargetLowering()
1782 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom); in X86TargetLowering()
1784 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Legal); in X86TargetLowering()
1786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom); in X86TargetLowering()
1788 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i16, Custom); in X86TargetLowering()
1790 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom); in X86TargetLowering()
[all …]
DX86ISelDAGToDAG.cpp4039 case MVT::v32i16: in getVPTESTMOpc()
4086 case MVT::v32i16: in getVPTESTMOpc()
4116 case MVT::v32i16: in getVPTESTMOpc()
4163 case MVT::v32i16: in getVPTESTMOpc()
DX86FastISel.cpp456 case MVT::v32i16: in X86FastEmitLoad()
628 case MVT::v32i16: in X86FastEmitStore()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc931 LocVT == MVT::v32i16 ||
1018 LocVT == MVT::v32i16 ||
1147 LocVT == MVT::v32i16 ||
1203 LocVT == MVT::v32i16 ||
1267 LocVT == MVT::v32i16 ||
1580 LocVT == MVT::v32i16 ||
1638 LocVT == MVT::v32i16 ||
1715 LocVT == MVT::v32i16 ||
2003 LocVT == MVT::v32i16 ||
2090 LocVT == MVT::v32i16 ||
[all …]
DX86GenGlobalISel.inc1591 …{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPADDWZrr:{ *:[v32i16…
2135 …{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPSUBWZrr:{ *:[v32i16…
2533 …{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMULLWZrr:{ *:[v32i1…
3966 …{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPANDQZrr:{ *:[v32i16…
5540 …:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPORQZrr:{ *:[v32i16…
6862 …{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPXORQZrr:{ *:[v32i16…
10636 …// (anyext:{ *:[v32i16] } VK32:{ *:[v32i1] }:$src) => (VPMOVM2WZrr:{ *:[v32i16] } VK32:{ *:[v32i…
10828 …// (trunc:{ *:[v32i8] } VR512:{ *:[v32i16] }:$src) => (VPMOVWBZrr:{ *:[v32i8] } VR512:{ *:[v32i1…
11430 …// (sext:{ *:[v32i16] } VR256X:{ *:[v32i8] }:$src) => (VPMOVSXBWZrr:{ *:[v32i16] } VR256X:{ *:[v…
11441 …// (sext:{ *:[v32i16] } VK32:{ *:[v32i1] }:$src) => (VPMOVM2WZrr:{ *:[v32i16] } VK32:{ *:[v32i1]…
[all …]
DX86GenFastISel.inc106 if (RetVT.SimpleTy != MVT::v32i16)
184 case MVT::v32i16: return fastEmit_ISD_ABS_MVT_v32i16_r(RetVT, Op0, Op0IsKill);
311 case MVT::v32i16: return fastEmit_ISD_ANY_EXTEND_MVT_v32i1_MVT_v32i16_r(Op0, Op0IsKill);
692 if (RetVT.SimpleTy != MVT::v32i16)
764 case MVT::v32i16: return fastEmit_ISD_CTPOP_MVT_v32i16_r(RetVT, Op0, Op0IsKill);
1436 case MVT::v32i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v32i1_MVT_v32i16_r(Op0, Op0IsKill);
1476 if (RetVT.SimpleTy != MVT::v32i16)
2642 case MVT::v32i16: return fastEmit_ISD_TRUNCATE_MVT_v32i16_r(RetVT, Op0, Op0IsKill);
2811 if (RetVT.SimpleTy != MVT::v32i16)
5952 case MVT::v32i16: return fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v32i16_r(Op0, Op0IsKill);
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp185 case MVT::v32i16: return VectorType::get(Type::getInt16Ty(Context), 32); in getTypeForEVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td63 def v32i16 : ValueType<512, 40>; // 32 x i16 vector value
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsics.td253 def llvm_v32i16_ty : LLVMType<v32i16>; // 32 x i16
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp114 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Custom); in R600TargetLowering()

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