Searched refs:work_reg_count (Results 1 – 11 of 11) sorted by relevance
63 pan_register_allocation(unsigned work_reg_count) in pan_register_allocation() argument65 return (work_reg_count <= 32) ? in pan_register_allocation()93 rsd->properties.work_register_count = info->work_reg_count; in pan_shader_prepare_midgard_rsd()178 pan_register_allocation(info->work_reg_count); in pan_shader_prepare_bifrost_rsd()
90 unsigned work_reg_count; member
842 variant->work_reg_count = info.work_reg_count; in GENX()
392 assert(b->work_reg_count <= full_threads); in pan_blitter_get_blend_shaders()
102 ctx->info->work_reg_count = MAX2(ctx->info->work_reg_count, r.reg + 1); in index_to_reg()714 ctx->info->work_reg_count = MAX2(ctx->info->work_reg_count, 3); in allocate_registers()
3362 unsigned nr_registers = info->work_reg_count; in midgard_compile_shader_nir()
275 unsigned work_reg_count; member
870 ctx->info.work_reg_count = 32; in bi_register_allocate()882 ctx->info.work_reg_count = 64; in bi_register_allocate()
4176 bool full_threads = (ctx->arch == 7 && ctx->info.work_reg_count <= 32); in bi_print_stats()4238 unsigned nr_threads = (ctx->info.work_reg_count <= 32) ? 2 : 1; in va_print_stats()5245 info->vs.secondary_work_reg_count = ctx->info.work_reg_count; in bi_compile_variant()5248 info->work_reg_count = ctx->info.work_reg_count; in bi_compile_variant()
749 unsigned work_reg_count; member
556 … cfg.properties.work_register_count = MAX2(fs->info.work_reg_count, 8); in panfrost_prepare_fs_state()558 cfg.properties.work_register_count = fs->info.work_reg_count; in panfrost_prepare_fs_state()4567 cfg.register_allocation = pan_register_allocation(state->info.work_reg_count); in prepare_shader()4582 cfg.register_allocation = pan_register_allocation(state->info.work_reg_count); in prepare_shader()