| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.h | 60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
66 SRII(MODULO, DP_DTO, 0),\
67 SRII(MODULO, DP_DTO, 1),\
68 SRII(MODULO, DP_DTO, 2),\
69 SRII(MODULO, DP_DTO, 3),\
[all …]
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| D | dce_hwseq.h | 39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_mpc.h | 47 SRII(MPCC_TOP_GAIN, MPCC, inst),\
48 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
49 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
50 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
51 SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
52 SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \
53 SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),\
54 SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),\
55 SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst),\
56 SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst),\
[all …]
|
| D | dcn30_resource.c | 261 #define SRII(reg_name, block, id)\ macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_mpc.h | 35 SRII(MPCC_TOP_GAIN, MPCC, inst),\
36 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
37 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
38 SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
39 SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
40 SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
41 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
42 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
43 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\
44 SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
[all …]
|
| D | dcn20_dwb.h | 49 #define SRII(reg_name, block, id)\ macro
|
| D | dcn20_resource.c | 503 #define SRII(reg_name, block, id)\ macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_mpc.h | 34 SRII(MPCC_TOP_SEL, MPCC, inst),\
35 SRII(MPCC_BOT_SEL, MPCC, inst),\
36 SRII(MPCC_CONTROL, MPCC, inst),\
37 SRII(MPCC_STATUS, MPCC, inst),\
38 SRII(MPCC_OPP_ID, MPCC, inst),\
39 SRII(MPCC_BG_G_Y, MPCC, inst),\
40 SRII(MPCC_BG_R_CR, MPCC, inst),\
41 SRII(MPCC_BG_B_CB, MPCC, inst),\
42 SRII(MPCC_SM_CONTROL, MPCC, inst),\
43 SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
[all …]
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| D | dcn10_dwb.h | 45 #define SRII(reg_name, block, id)\ macro
|
| D | dcn10_resource.c | 181 #define SRII(reg_name, block, id)\ macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 494 #define SRII(reg_name, block, id)\ macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 780 #define SRII(reg_name, block, id)\ macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 612 #define SRII(reg_name, block, id)\ macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 617 #define SRII(reg_name, block, id)\ macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 524 #define SRII(reg_name, block, id)\ macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 548 #define SRII(reg_name, block, id)\ macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 336 #define SRII(reg_name, block, id)\ macro
|