| /kernel/linux/linux-5.10/drivers/reset/sti/ |
| D | reset-stih407.c | 18 #define STIH407_PDN_0(_bit) \ argument
19 _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
20 #define STIH407_PDN_1(_bit) \ argument
21 _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
22 #define STIH407_PDN_ETH(_bit, _stat) \ argument
23 _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
58 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
61 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/meson/ |
| D | clk-regmap.h | 117 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
121 .bit_idx = (_bit), \
132 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
133 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
135 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
136 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
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| D | gxbb-aoclk.c | 23 #define GXBB_AO_GATE(_name, _bit) \ argument
27 .bit_idx = (_bit), \
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| D | axg-aoclk.c | 34 #define AXG_AO_GATE(_name, _bit) \ argument
38 .bit_idx = (_bit), \
|
| /kernel/linux/linux-5.10/arch/arc/include/asm/ |
| D | bitops.h | 29 static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
60 static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
107 static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
124 static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
146 static inline void __##op##_bit(unsigned long nr, volatile unsigned long *m) \
156 static inline int __test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
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| /kernel/linux/linux-5.10/arch/xtensa/include/asm/ |
| D | bitops.h | 102 static inline void op##_bit(unsigned int bit, volatile unsigned long *p)\
122 test_and_##op##_bit(unsigned int bit, volatile unsigned long *p) \
145 static inline void op##_bit(unsigned int bit, volatile unsigned long *p)\
166 test_and_##op##_bit(unsigned int bit, volatile unsigned long *p) \
|
| /kernel/linux/linux-5.10/drivers/pinctrl/mediatek/ |
| D | pinctrl-mtk-common.h | 109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
113 .bit = _bit, \
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
161 .bit = _bit, \
|
| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-kona.h | 99 #define POLICY(_offset, _bit) \ argument
102 .bit = (_bit), \
383 #define TRIGGER(_offset, _bit) \ argument
386 .bit = (_bit), \
442 #define CCU_LVM_EN(_offset, _bit) \ argument
445 .bit = (_bit), \
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| /kernel/linux/linux-5.10/Documentation/ |
| D | atomic_bitops.txt | 20 {set,clear,change}_bit()
25 test_and_{set,clear,change}_bit()
47 The test_and_{}_bit() operations return the original value of the bit.
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| /kernel/linux/linux-5.10/drivers/reset/ |
| D | reset-uniphier.c | 28 #define UNIPHIER_RESET(_id, _reg, _bit) \ argument
32 .bit = (_bit), \
35 #define UNIPHIER_RESETX(_id, _reg, _bit) \ argument
39 .bit = (_bit), \
|
| /kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7366.c | 108 #define DIV4(_reg, _bit, _mask, _flags) \ argument
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
128 #define MSTP(_parent, _reg, _bit, _flags) \ argument
129 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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| D | clock-sh7343.c | 105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
125 #define MSTP(_parent, _reg, _bit, _flags) \ argument
126 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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| D | clock-sh7757.c | 62 #define DIV4(_bit, _mask, _flags) \ argument
63 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
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| D | clock-shx3.c | 61 #define DIV4(_bit, _mask, _flags) \ argument
62 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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| D | clock-sh7785.c | 66 #define DIV4(_bit, _mask, _flags) \ argument
67 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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| D | clock-sh7786.c | 67 #define DIV4(_bit, _mask, _flags) \ argument
68 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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| /kernel/linux/linux-5.10/drivers/clk/mvebu/ |
| D | armada-37xx-periph.c | 129 #define PERIPH_GATE(_name, _bit) \ argument
132 .bit_idx = _bit, \
181 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
182 static PERIPH_GATE(_name, _bit); \
186 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
187 static PERIPH_GATE(_name, _bit); \
191 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
192 static PERIPH_GATE(_name, _bit); \
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| /kernel/linux/linux-5.10/drivers/clk/uniphier/ |
| D | clk-uniphier.h | 95 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ argument
103 .bit = (_bit), \
|
| /kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh2a/ |
| D | clock-sh7264.c | 77 #define DIV4(_reg, _bit, _mask, _flags) \ argument
78 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| D | clock-sh7269.c | 105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| /kernel/linux/linux-5.10/drivers/clk/zte/ |
| D | clk.h | 60 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
64 .bit_idx = (_bit), \
|
| /kernel/linux/linux-5.10/drivers/memory/tegra/ |
| D | tegra20.c | 170 #define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit) \ argument
177 .bit = _bit, \
|
| /kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/ |
| D | odm_interface.h | 40 #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
|
| /kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
| D | fw.h | 318 #define FW_CMD_IO_CLR(rtlpriv, _bit) \ argument
321 rtlpriv->rtlhal.fwcmd_iomap &= (~_bit); \
|
| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-oxnas.c | 89 #define OXNAS_GATE(_name, _bit, _parents) \ argument
91 .bit = (_bit), \
|