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1 # SPDX-License-Identifier: GPL-2.0
2 config ARM
3 	bool
4 	default y
5 	select ARCH_32BIT_OFF_T
6 	select ARCH_HAS_BINFMT_FLAT
7 	select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 	select ARCH_HAS_DEVMEM_IS_ALLOWED
9 	select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
10 	select ARCH_HAS_ELF_RANDOMIZE
11 	select ARCH_HAS_FORTIFY_SOURCE
12 	select ARCH_HAS_KEEPINITRD
13 	select ARCH_HAS_KCOV
14 	select ARCH_HAS_MEMBARRIER_SYNC_CORE
15 	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
16 	select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
17 	select ARCH_HAS_PHYS_TO_DMA
18 	select ARCH_HAS_SETUP_DMA_OPS
19 	select ARCH_HAS_SET_MEMORY
20 	select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
21 	select ARCH_HAS_STRICT_MODULE_RWX if MMU
22 	select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
23 	select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
24 	select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
25 	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
26 	select ARCH_HAVE_CUSTOM_GPIO_H
27 	select ARCH_HAS_GCOV_PROFILE_ALL
28 	select ARCH_KEEP_MEMBLOCK
29 	select ARCH_MIGHT_HAVE_PC_PARPORT
30 	select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 	select ARCH_SUPPORTS_ATOMIC_RMW
34 	select ARCH_USE_BUILTIN_BSWAP
35 	select ARCH_USE_CMPXCHG_LOCKREF
36 	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
37 	select ARCH_WANT_IPC_PARSE_VERSION
38 	select ARCH_WANT_LD_ORPHAN_WARN
39 	select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
40 	select BUILDTIME_TABLE_SORT if MMU
41 	select CLONE_BACKWARDS
42 	select CPU_PM if SUSPEND || CPU_IDLE
43 	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
44 	select DMA_DECLARE_COHERENT
45 	select DMA_OPS
46 	select DMA_REMAP if MMU
47 	select EDAC_SUPPORT
48 	select EDAC_ATOMIC_SCRUB
49 	select GENERIC_ALLOCATOR
50 	select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
51 	select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
52 	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
53 	select GENERIC_IRQ_IPI if SMP
54 	select GENERIC_CPU_AUTOPROBE
55 	select GENERIC_EARLY_IOREMAP
56 	select GENERIC_IDLE_POLL_SETUP
57 	select GENERIC_IRQ_PROBE
58 	select GENERIC_IRQ_SHOW
59 	select GENERIC_IRQ_SHOW_LEVEL
60 	select GENERIC_PCI_IOMAP
61 	select GENERIC_SCHED_CLOCK
62 	select GENERIC_SMP_IDLE_THREAD
63 	select GENERIC_STRNCPY_FROM_USER
64 	select GENERIC_STRNLEN_USER
65 	select HANDLE_DOMAIN_IRQ
66 	select HARDIRQS_SW_RESEND
67 	select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
68 	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
69 	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
70 	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
71 	select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
72 	select HAVE_ARCH_MMAP_RND_BITS if MMU
73 	select HAVE_ARCH_SECCOMP
74 	select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
75 	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
76 	select HAVE_ARCH_TRACEHOOK
77 	select HAVE_ARM_SMCCC if CPU_V7
78 	select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
79 	select HAVE_CONTEXT_TRACKING
80 	select HAVE_C_RECORDMCOUNT
81 	select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
82 	select HAVE_DMA_CONTIGUOUS if MMU
83 	select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
84 	select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
85 	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
86 	select HAVE_EXIT_THREAD
87 	select HAVE_FAST_GUP if ARM_LPAE
88 	select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
89 	select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
90 	select HAVE_FUNCTION_TRACER if !XIP_KERNEL
91 	select HAVE_FUTEX_CMPXCHG if FUTEX
92 	select HAVE_GCC_PLUGINS
93 	select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
94 	select HAVE_IDE if PCI || ISA || PCMCIA
95 	select HAVE_IRQ_TIME_ACCOUNTING
96 	select HAVE_KERNEL_GZIP
97 	select HAVE_KERNEL_LZ4
98 	select HAVE_KERNEL_LZMA
99 	select HAVE_KERNEL_LZO
100 	select HAVE_KERNEL_XZ
101 	select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
102 	select HAVE_KRETPROBES if HAVE_KPROBES
103 	select HAVE_MOD_ARCH_SPECIFIC
104 	select HAVE_NMI
105 	select HAVE_OPROFILE if HAVE_PERF_EVENTS
106 	select HAVE_OPTPROBES if !THUMB2_KERNEL
107 	select HAVE_PERF_EVENTS
108 	select HAVE_PERF_REGS
109 	select HAVE_PERF_USER_STACK_DUMP
110 	select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
111 	select HAVE_REGS_AND_STACK_ACCESS_API
112 	select HAVE_RSEQ
113 	select HAVE_STACKPROTECTOR
114 	select HAVE_SYSCALL_TRACEPOINTS
115 	select HAVE_UID16
116 	select HAVE_VIRT_CPU_ACCOUNTING_GEN
117 	select IRQ_FORCED_THREADING
118 	select MODULES_USE_ELF_REL
119 	select NEED_DMA_MAP_STATE
120 	select OF_EARLY_FLATTREE if OF
121 	select OLD_SIGACTION
122 	select OLD_SIGSUSPEND3
123 	select PCI_SYSCALL if PCI
124 	select PERF_USE_VMALLOC
125 	select RTC_LIB
126 	select SET_FS
127 	select SYS_SUPPORTS_APM_EMULATION
128 	# Above selects are sorted alphabetically; please add new ones
129 	# according to that.  Thanks.
130 	help
131 	  The ARM series is a line of low-power-consumption RISC chip designs
132 	  licensed by ARM Ltd and targeted at embedded applications and
133 	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
134 	  manufactured, but legacy ARM-based PC hardware remains popular in
135 	  Europe.  There is an ARM Linux project with a web page at
136 	  <http://www.arm.linux.org.uk/>.
137 
138 config ARM_HAS_SG_CHAIN
139 	bool
140 
141 config ARM_DMA_USE_IOMMU
142 	bool
143 	select ARM_HAS_SG_CHAIN
144 	select NEED_SG_DMA_LENGTH
145 
146 if ARM_DMA_USE_IOMMU
147 
148 config ARM_DMA_IOMMU_ALIGNMENT
149 	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
150 	range 4 9
151 	default 8
152 	help
153 	  DMA mapping framework by default aligns all buffers to the smallest
154 	  PAGE_SIZE order which is greater than or equal to the requested buffer
155 	  size. This works well for buffers up to a few hundreds kilobytes, but
156 	  for larger buffers it just a waste of address space. Drivers which has
157 	  relatively small addressing window (like 64Mib) might run out of
158 	  virtual space with just a few allocations.
159 
160 	  With this parameter you can specify the maximum PAGE_SIZE order for
161 	  DMA IOMMU buffers. Larger buffers will be aligned only to this
162 	  specified order. The order is expressed as a power of two multiplied
163 	  by the PAGE_SIZE.
164 
165 endif
166 
167 config SYS_SUPPORTS_APM_EMULATION
168 	bool
169 
170 config HAVE_TCM
171 	bool
172 	select GENERIC_ALLOCATOR
173 
174 config HAVE_PROC_CPU
175 	bool
176 
177 config NO_IOPORT_MAP
178 	bool
179 
180 config SBUS
181 	bool
182 
183 config STACKTRACE_SUPPORT
184 	bool
185 	default y
186 
187 config LOCKDEP_SUPPORT
188 	bool
189 	default y
190 
191 config TRACE_IRQFLAGS_SUPPORT
192 	bool
193 	default !CPU_V7M
194 
195 config ARCH_HAS_ILOG2_U32
196 	bool
197 
198 config ARCH_HAS_ILOG2_U64
199 	bool
200 
201 config ARCH_HAS_BANDGAP
202 	bool
203 
204 config FIX_EARLYCON_MEM
205 	def_bool y if MMU
206 
207 config GENERIC_HWEIGHT
208 	bool
209 	default y
210 
211 config GENERIC_CALIBRATE_DELAY
212 	bool
213 	default y
214 
215 config ARCH_MAY_HAVE_PC_FDC
216 	bool
217 
218 config ZONE_DMA
219 	bool
220 
221 config ARCH_SUPPORTS_UPROBES
222 	def_bool y
223 
224 config ARCH_HAS_DMA_SET_COHERENT_MASK
225 	bool
226 
227 config GENERIC_ISA_DMA
228 	bool
229 
230 config FIQ
231 	bool
232 
233 config NEED_RET_TO_USER
234 	bool
235 
236 config ARCH_MTD_XIP
237 	bool
238 
239 config ARM_PATCH_PHYS_VIRT
240 	bool "Patch physical to virtual translations at runtime" if EMBEDDED
241 	default y
242 	depends on !XIP_KERNEL && MMU
243 	help
244 	  Patch phys-to-virt and virt-to-phys translation functions at
245 	  boot and module load time according to the position of the
246 	  kernel in system memory.
247 
248 	  This can only be used with non-XIP MMU kernels where the base
249 	  of physical memory is at a 2 MiB boundary.
250 
251 	  Only disable this option if you know that you do not require
252 	  this feature (eg, building a kernel for a single machine) and
253 	  you need to shrink the kernel to the minimal size.
254 
255 config NEED_MACH_IO_H
256 	bool
257 	help
258 	  Select this when mach/io.h is required to provide special
259 	  definitions for this platform.  The need for mach/io.h should
260 	  be avoided when possible.
261 
262 config NEED_MACH_MEMORY_H
263 	bool
264 	help
265 	  Select this when mach/memory.h is required to provide special
266 	  definitions for this platform.  The need for mach/memory.h should
267 	  be avoided when possible.
268 
269 config PHYS_OFFSET
270 	hex "Physical address of main memory" if MMU
271 	depends on !ARM_PATCH_PHYS_VIRT
272 	default DRAM_BASE if !MMU
273 	default 0x00000000 if ARCH_EBSA110 || \
274 			ARCH_FOOTBRIDGE
275 	default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
276 	default 0x20000000 if ARCH_S5PV210
277 	default 0xc0000000 if ARCH_SA1100
278 	help
279 	  Please provide the physical address corresponding to the
280 	  location of main memory in your system.
281 
282 config GENERIC_BUG
283 	def_bool y
284 	depends on BUG
285 
286 config PGTABLE_LEVELS
287 	int
288 	default 3 if ARM_LPAE
289 	default 2
290 
291 menu "System Type"
292 
293 config MMU
294 	bool "MMU-based Paged Memory Management Support"
295 	default y
296 	help
297 	  Select if you want MMU-based virtualised addressing space
298 	  support by paged memory management. If unsure, say 'Y'.
299 
300 config ARCH_MMAP_RND_BITS_MIN
301 	default 8
302 
303 config ARCH_MMAP_RND_BITS_MAX
304 	default 14 if PAGE_OFFSET=0x40000000
305 	default 15 if PAGE_OFFSET=0x80000000
306 	default 16
307 
308 #
309 # The "ARM system type" choice list is ordered alphabetically by option
310 # text.  Please add new entries in the option alphabetic order.
311 #
312 choice
313 	prompt "ARM system type"
314 	default ARM_SINGLE_ARMV7M if !MMU
315 	default ARCH_MULTIPLATFORM if MMU
316 
317 config ARCH_MULTIPLATFORM
318 	bool "Allow multiple platforms to be selected"
319 	depends on MMU
320 	select ARCH_FLATMEM_ENABLE
321 	select ARCH_SPARSEMEM_ENABLE
322 	select ARCH_SELECT_MEMORY_MODEL
323 	select ARM_HAS_SG_CHAIN
324 	select ARM_PATCH_PHYS_VIRT
325 	select AUTO_ZRELADDR
326 	select TIMER_OF
327 	select COMMON_CLK
328 	select GENERIC_CLOCKEVENTS
329 	select GENERIC_IRQ_MULTI_HANDLER
330 	select HAVE_PCI
331 	select PCI_DOMAINS_GENERIC if PCI
332 	select SPARSE_IRQ
333 	select USE_OF
334 
335 config ARM_SINGLE_ARMV7M
336 	bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
337 	depends on !MMU
338 	select ARM_NVIC
339 	select AUTO_ZRELADDR
340 	select TIMER_OF
341 	select COMMON_CLK
342 	select CPU_V7M
343 	select GENERIC_CLOCKEVENTS
344 	select NO_IOPORT_MAP
345 	select SPARSE_IRQ
346 	select USE_OF
347 
348 config ARCH_EBSA110
349 	bool "EBSA-110"
350 	select ARCH_USES_GETTIMEOFFSET
351 	select CPU_SA110
352 	select ISA
353 	select NEED_MACH_IO_H
354 	select NEED_MACH_MEMORY_H
355 	select NO_IOPORT_MAP
356 	help
357 	  This is an evaluation board for the StrongARM processor available
358 	  from Digital. It has limited hardware on-board, including an
359 	  Ethernet interface, two PCMCIA sockets, two serial ports and a
360 	  parallel port.
361 
362 config ARCH_EP93XX
363 	bool "EP93xx-based"
364 	select ARCH_SPARSEMEM_ENABLE
365 	select ARM_AMBA
366 	imply ARM_PATCH_PHYS_VIRT
367 	select ARM_VIC
368 	select AUTO_ZRELADDR
369 	select CLKDEV_LOOKUP
370 	select CLKSRC_MMIO
371 	select CPU_ARM920T
372 	select GENERIC_CLOCKEVENTS
373 	select GPIOLIB
374 	select HAVE_LEGACY_CLK
375 	help
376 	  This enables support for the Cirrus EP93xx series of CPUs.
377 
378 config ARCH_FOOTBRIDGE
379 	bool "FootBridge"
380 	select CPU_SA110
381 	select FOOTBRIDGE
382 	select GENERIC_CLOCKEVENTS
383 	select HAVE_IDE
384 	select NEED_MACH_IO_H if !MMU
385 	select NEED_MACH_MEMORY_H
386 	help
387 	  Support for systems based on the DC21285 companion chip
388 	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
389 
390 config ARCH_IOP32X
391 	bool "IOP32x-based"
392 	depends on MMU
393 	select CPU_XSCALE
394 	select GPIO_IOP
395 	select GPIOLIB
396 	select NEED_RET_TO_USER
397 	select FORCE_PCI
398 	select PLAT_IOP
399 	help
400 	  Support for Intel's 80219 and IOP32X (XScale) family of
401 	  processors.
402 
403 config ARCH_IXP4XX
404 	bool "IXP4xx-based"
405 	depends on MMU
406 	select ARCH_HAS_DMA_SET_COHERENT_MASK
407 	select ARCH_SUPPORTS_BIG_ENDIAN
408 	select CPU_XSCALE
409 	select DMABOUNCE if PCI
410 	select GENERIC_CLOCKEVENTS
411 	select GENERIC_IRQ_MULTI_HANDLER
412 	select GPIO_IXP4XX
413 	select GPIOLIB
414 	select HAVE_PCI
415 	select IXP4XX_IRQ
416 	select IXP4XX_TIMER
417 	select NEED_MACH_IO_H
418 	select USB_EHCI_BIG_ENDIAN_DESC
419 	select USB_EHCI_BIG_ENDIAN_MMIO
420 	help
421 	  Support for Intel's IXP4XX (XScale) family of processors.
422 
423 config ARCH_DOVE
424 	bool "Marvell Dove"
425 	select CPU_PJ4
426 	select GENERIC_CLOCKEVENTS
427 	select GENERIC_IRQ_MULTI_HANDLER
428 	select GPIOLIB
429 	select HAVE_PCI
430 	select MVEBU_MBUS
431 	select PINCTRL
432 	select PINCTRL_DOVE
433 	select PLAT_ORION_LEGACY
434 	select SPARSE_IRQ
435 	select PM_GENERIC_DOMAINS if PM
436 	help
437 	  Support for the Marvell Dove SoC 88AP510
438 
439 config ARCH_PXA
440 	bool "PXA2xx/PXA3xx-based"
441 	depends on MMU
442 	select ARCH_MTD_XIP
443 	select ARM_CPU_SUSPEND if PM
444 	select AUTO_ZRELADDR
445 	select COMMON_CLK
446 	select CLKSRC_PXA
447 	select CLKSRC_MMIO
448 	select TIMER_OF
449 	select CPU_XSCALE if !CPU_XSC3
450 	select GENERIC_CLOCKEVENTS
451 	select GENERIC_IRQ_MULTI_HANDLER
452 	select GPIO_PXA
453 	select GPIOLIB
454 	select HAVE_IDE
455 	select IRQ_DOMAIN
456 	select PLAT_PXA
457 	select SPARSE_IRQ
458 	help
459 	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
460 
461 config ARCH_RPC
462 	bool "RiscPC"
463 	depends on MMU
464 	select ARCH_ACORN
465 	select ARCH_MAY_HAVE_PC_FDC
466 	select ARCH_SPARSEMEM_ENABLE
467 	select ARM_HAS_SG_CHAIN
468 	select CPU_SA110
469 	select FIQ
470 	select HAVE_IDE
471 	select HAVE_PATA_PLATFORM
472 	select ISA_DMA_API
473 	select NEED_MACH_IO_H
474 	select NEED_MACH_MEMORY_H
475 	select NO_IOPORT_MAP
476 	help
477 	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
478 	  CD-ROM interface, serial and parallel port, and the floppy drive.
479 
480 config ARCH_SA1100
481 	bool "SA1100-based"
482 	select ARCH_MTD_XIP
483 	select ARCH_SPARSEMEM_ENABLE
484 	select CLKSRC_MMIO
485 	select CLKSRC_PXA
486 	select TIMER_OF if OF
487 	select COMMON_CLK
488 	select CPU_FREQ
489 	select CPU_SA1100
490 	select GENERIC_CLOCKEVENTS
491 	select GENERIC_IRQ_MULTI_HANDLER
492 	select GPIOLIB
493 	select HAVE_IDE
494 	select IRQ_DOMAIN
495 	select ISA
496 	select NEED_MACH_MEMORY_H
497 	select SPARSE_IRQ
498 	help
499 	  Support for StrongARM 11x0 based boards.
500 
501 config ARCH_S3C24XX
502 	bool "Samsung S3C24XX SoCs"
503 	select ATAGS
504 	select CLKSRC_SAMSUNG_PWM
505 	select GENERIC_CLOCKEVENTS
506 	select GPIO_SAMSUNG
507 	select GPIOLIB
508 	select GENERIC_IRQ_MULTI_HANDLER
509 	select HAVE_S3C2410_I2C if I2C
510 	select HAVE_S3C_RTC if RTC_CLASS
511 	select NEED_MACH_IO_H
512 	select S3C2410_WATCHDOG
513 	select SAMSUNG_ATAGS
514 	select USE_OF
515 	select WATCHDOG
516 	help
517 	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
518 	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
519 	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
520 	  Samsung SMDK2410 development board (and derivatives).
521 
522 config ARCH_OMAP1
523 	bool "TI OMAP1"
524 	depends on MMU
525 	select ARCH_OMAP
526 	select CLKDEV_LOOKUP
527 	select CLKSRC_MMIO
528 	select GENERIC_CLOCKEVENTS
529 	select GENERIC_IRQ_CHIP
530 	select GENERIC_IRQ_MULTI_HANDLER
531 	select GPIOLIB
532 	select HAVE_IDE
533 	select HAVE_LEGACY_CLK
534 	select IRQ_DOMAIN
535 	select NEED_MACH_IO_H if PCCARD
536 	select NEED_MACH_MEMORY_H
537 	select SPARSE_IRQ
538 	help
539 	  Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
540 
541 endchoice
542 
543 menu "Multiple platform selection"
544 	depends on ARCH_MULTIPLATFORM
545 
546 comment "CPU Core family selection"
547 
548 config ARCH_MULTI_V4
549 	bool "ARMv4 based platforms (FA526)"
550 	depends on !ARCH_MULTI_V6_V7
551 	select ARCH_MULTI_V4_V5
552 	select CPU_FA526
553 
554 config ARCH_MULTI_V4T
555 	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
556 	depends on !ARCH_MULTI_V6_V7
557 	select ARCH_MULTI_V4_V5
558 	select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
559 		CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
560 		CPU_ARM925T || CPU_ARM940T)
561 
562 config ARCH_MULTI_V5
563 	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
564 	depends on !ARCH_MULTI_V6_V7
565 	select ARCH_MULTI_V4_V5
566 	select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
567 		CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
568 		CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
569 
570 config ARCH_MULTI_V4_V5
571 	bool
572 
573 config ARCH_MULTI_V6
574 	bool "ARMv6 based platforms (ARM11)"
575 	select ARCH_MULTI_V6_V7
576 	select CPU_V6K
577 
578 config ARCH_MULTI_V7
579 	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
580 	default y
581 	select ARCH_MULTI_V6_V7
582 	select CPU_V7
583 	select HAVE_SMP
584 
585 config ARCH_MULTI_V6_V7
586 	bool
587 	select MIGHT_HAVE_CACHE_L2X0
588 
589 config ARCH_MULTI_CPU_AUTO
590 	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
591 	select ARCH_MULTI_V5
592 
593 endmenu
594 
595 config ARCH_VIRT
596 	bool "Dummy Virtual Machine"
597 	depends on ARCH_MULTI_V7
598 	select ARM_AMBA
599 	select ARM_GIC
600 	select ARM_GIC_V2M if PCI
601 	select ARM_GIC_V3
602 	select ARM_GIC_V3_ITS if PCI
603 	select ARM_PSCI
604 	select HAVE_ARM_ARCH_TIMER
605 	select ARCH_SUPPORTS_BIG_ENDIAN
606 
607 #
608 # This is sorted alphabetically by mach-* pathname.  However, plat-*
609 # Kconfigs may be included either alphabetically (according to the
610 # plat- suffix) or along side the corresponding mach-* source.
611 #
612 source "arch/arm/mach-actions/Kconfig"
613 
614 source "arch/arm/mach-alpine/Kconfig"
615 
616 source "arch/arm/mach-artpec/Kconfig"
617 
618 source "arch/arm/mach-asm9260/Kconfig"
619 
620 source "arch/arm/mach-aspeed/Kconfig"
621 
622 source "arch/arm/mach-at91/Kconfig"
623 
624 source "arch/arm/mach-axxia/Kconfig"
625 
626 source "arch/arm/mach-bcm/Kconfig"
627 
628 source "arch/arm/mach-berlin/Kconfig"
629 
630 source "arch/arm/mach-clps711x/Kconfig"
631 
632 source "arch/arm/mach-cns3xxx/Kconfig"
633 
634 source "arch/arm/mach-davinci/Kconfig"
635 
636 source "arch/arm/mach-digicolor/Kconfig"
637 
638 source "arch/arm/mach-dove/Kconfig"
639 
640 source "arch/arm/mach-ep93xx/Kconfig"
641 
642 source "arch/arm/mach-exynos/Kconfig"
643 
644 source "arch/arm/mach-footbridge/Kconfig"
645 
646 source "arch/arm/mach-gemini/Kconfig"
647 
648 source "arch/arm/mach-highbank/Kconfig"
649 
650 source "arch/arm/mach-hisi/Kconfig"
651 
652 source "arch/arm/mach-imx/Kconfig"
653 
654 source "arch/arm/mach-integrator/Kconfig"
655 
656 source "arch/arm/mach-iop32x/Kconfig"
657 
658 source "arch/arm/mach-ixp4xx/Kconfig"
659 
660 source "arch/arm/mach-keystone/Kconfig"
661 
662 source "arch/arm/mach-lpc32xx/Kconfig"
663 
664 source "arch/arm/mach-mediatek/Kconfig"
665 
666 source "arch/arm/mach-meson/Kconfig"
667 
668 source "arch/arm/mach-milbeaut/Kconfig"
669 
670 source "arch/arm/mach-mmp/Kconfig"
671 
672 source "arch/arm/mach-moxart/Kconfig"
673 
674 source "arch/arm/mach-mstar/Kconfig"
675 
676 source "arch/arm/mach-mv78xx0/Kconfig"
677 
678 source "arch/arm/mach-mvebu/Kconfig"
679 
680 source "arch/arm/mach-mxs/Kconfig"
681 
682 source "arch/arm/mach-nomadik/Kconfig"
683 
684 source "arch/arm/mach-npcm/Kconfig"
685 
686 source "arch/arm/mach-nspire/Kconfig"
687 
688 source "arch/arm/plat-omap/Kconfig"
689 
690 source "arch/arm/mach-omap1/Kconfig"
691 
692 source "arch/arm/mach-omap2/Kconfig"
693 
694 source "arch/arm/mach-orion5x/Kconfig"
695 
696 source "arch/arm/mach-oxnas/Kconfig"
697 
698 source "arch/arm/mach-picoxcell/Kconfig"
699 
700 source "arch/arm/mach-prima2/Kconfig"
701 
702 source "arch/arm/mach-pxa/Kconfig"
703 source "arch/arm/plat-pxa/Kconfig"
704 
705 source "arch/arm/mach-qcom/Kconfig"
706 
707 source "arch/arm/mach-rda/Kconfig"
708 
709 source "arch/arm/mach-realtek/Kconfig"
710 
711 source "arch/arm/mach-realview/Kconfig"
712 
713 source "arch/arm/mach-rockchip/Kconfig"
714 
715 source "arch/arm/mach-s3c/Kconfig"
716 
717 source "arch/arm/mach-s5pv210/Kconfig"
718 
719 source "arch/arm/mach-sa1100/Kconfig"
720 
721 source "arch/arm/mach-shmobile/Kconfig"
722 
723 source "arch/arm/mach-socfpga/Kconfig"
724 
725 source "arch/arm/mach-spear/Kconfig"
726 
727 source "arch/arm/mach-sti/Kconfig"
728 
729 source "arch/arm/mach-stm32/Kconfig"
730 
731 source "arch/arm/mach-sunxi/Kconfig"
732 
733 source "arch/arm/mach-tango/Kconfig"
734 
735 source "arch/arm/mach-tegra/Kconfig"
736 
737 source "arch/arm/mach-u300/Kconfig"
738 
739 source "arch/arm/mach-uniphier/Kconfig"
740 
741 source "arch/arm/mach-ux500/Kconfig"
742 
743 source "arch/arm/mach-versatile/Kconfig"
744 
745 source "arch/arm/mach-vexpress/Kconfig"
746 
747 source "arch/arm/mach-vt8500/Kconfig"
748 
749 source "arch/arm/mach-zx/Kconfig"
750 
751 source "arch/arm/mach-zynq/Kconfig"
752 
753 # ARMv7-M architecture
754 config ARCH_EFM32
755 	bool "Energy Micro efm32"
756 	depends on ARM_SINGLE_ARMV7M
757 	select GPIOLIB
758 	help
759 	  Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
760 	  processors.
761 
762 config ARCH_LPC18XX
763 	bool "NXP LPC18xx/LPC43xx"
764 	depends on ARM_SINGLE_ARMV7M
765 	select ARCH_HAS_RESET_CONTROLLER
766 	select ARM_AMBA
767 	select CLKSRC_LPC32XX
768 	select PINCTRL
769 	help
770 	  Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
771 	  high performance microcontrollers.
772 
773 config ARCH_MPS2
774 	bool "ARM MPS2 platform"
775 	depends on ARM_SINGLE_ARMV7M
776 	select ARM_AMBA
777 	select CLKSRC_MPS2
778 	help
779 	  Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
780 	  with a range of available cores like Cortex-M3/M4/M7.
781 
782 	  Please, note that depends which Application Note is used memory map
783 	  for the platform may vary, so adjustment of RAM base might be needed.
784 
785 # Definitions to make life easier
786 config ARCH_ACORN
787 	bool
788 
789 config PLAT_IOP
790 	bool
791 	select GENERIC_CLOCKEVENTS
792 
793 config PLAT_ORION
794 	bool
795 	select CLKSRC_MMIO
796 	select COMMON_CLK
797 	select GENERIC_IRQ_CHIP
798 	select IRQ_DOMAIN
799 
800 config PLAT_ORION_LEGACY
801 	bool
802 	select PLAT_ORION
803 
804 config PLAT_PXA
805 	bool
806 
807 config PLAT_VERSATILE
808 	bool
809 
810 source "arch/arm/mm/Kconfig"
811 
812 config IWMMXT
813 	bool "Enable iWMMXt support"
814 	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
815 	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
816 	help
817 	  Enable support for iWMMXt context switching at run time if
818 	  running on a CPU that supports it.
819 
820 if !MMU
821 source "arch/arm/Kconfig-nommu"
822 endif
823 
824 config PJ4B_ERRATA_4742
825 	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
826 	depends on CPU_PJ4B && MACH_ARMADA_370
827 	default y
828 	help
829 	  When coming out of either a Wait for Interrupt (WFI) or a Wait for
830 	  Event (WFE) IDLE states, a specific timing sensitivity exists between
831 	  the retiring WFI/WFE instructions and the newly issued subsequent
832 	  instructions.  This sensitivity can result in a CPU hang scenario.
833 	  Workaround:
834 	  The software must insert either a Data Synchronization Barrier (DSB)
835 	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE
836 	  instruction
837 
838 config ARM_ERRATA_326103
839 	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
840 	depends on CPU_V6
841 	help
842 	  Executing a SWP instruction to read-only memory does not set bit 11
843 	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
844 	  treat the access as a read, preventing a COW from occurring and
845 	  causing the faulting task to livelock.
846 
847 config ARM_ERRATA_411920
848 	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
849 	depends on CPU_V6 || CPU_V6K
850 	help
851 	  Invalidation of the Instruction Cache operation can
852 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
853 	  It does not affect the MPCore. This option enables the ARM Ltd.
854 	  recommended workaround.
855 
856 config ARM_ERRATA_430973
857 	bool "ARM errata: Stale prediction on replaced interworking branch"
858 	depends on CPU_V7
859 	help
860 	  This option enables the workaround for the 430973 Cortex-A8
861 	  r1p* erratum. If a code sequence containing an ARM/Thumb
862 	  interworking branch is replaced with another code sequence at the
863 	  same virtual address, whether due to self-modifying code or virtual
864 	  to physical address re-mapping, Cortex-A8 does not recover from the
865 	  stale interworking branch prediction. This results in Cortex-A8
866 	  executing the new code sequence in the incorrect ARM or Thumb state.
867 	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
868 	  and also flushes the branch target cache at every context switch.
869 	  Note that setting specific bits in the ACTLR register may not be
870 	  available in non-secure mode.
871 
872 config ARM_ERRATA_458693
873 	bool "ARM errata: Processor deadlock when a false hazard is created"
874 	depends on CPU_V7
875 	depends on !ARCH_MULTIPLATFORM
876 	help
877 	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
878 	  erratum. For very specific sequences of memory operations, it is
879 	  possible for a hazard condition intended for a cache line to instead
880 	  be incorrectly associated with a different cache line. This false
881 	  hazard might then cause a processor deadlock. The workaround enables
882 	  the L1 caching of the NEON accesses and disables the PLD instruction
883 	  in the ACTLR register. Note that setting specific bits in the ACTLR
884 	  register may not be available in non-secure mode.
885 
886 config ARM_ERRATA_460075
887 	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
888 	depends on CPU_V7
889 	depends on !ARCH_MULTIPLATFORM
890 	help
891 	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
892 	  erratum. Any asynchronous access to the L2 cache may encounter a
893 	  situation in which recent store transactions to the L2 cache are lost
894 	  and overwritten with stale memory contents from external memory. The
895 	  workaround disables the write-allocate mode for the L2 cache via the
896 	  ACTLR register. Note that setting specific bits in the ACTLR register
897 	  may not be available in non-secure mode.
898 
899 config ARM_ERRATA_742230
900 	bool "ARM errata: DMB operation may be faulty"
901 	depends on CPU_V7 && SMP
902 	depends on !ARCH_MULTIPLATFORM
903 	help
904 	  This option enables the workaround for the 742230 Cortex-A9
905 	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
906 	  between two write operations may not ensure the correct visibility
907 	  ordering of the two writes. This workaround sets a specific bit in
908 	  the diagnostic register of the Cortex-A9 which causes the DMB
909 	  instruction to behave as a DSB, ensuring the correct behaviour of
910 	  the two writes.
911 
912 config ARM_ERRATA_742231
913 	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
914 	depends on CPU_V7 && SMP
915 	depends on !ARCH_MULTIPLATFORM
916 	help
917 	  This option enables the workaround for the 742231 Cortex-A9
918 	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
919 	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
920 	  accessing some data located in the same cache line, may get corrupted
921 	  data due to bad handling of the address hazard when the line gets
922 	  replaced from one of the CPUs at the same time as another CPU is
923 	  accessing it. This workaround sets specific bits in the diagnostic
924 	  register of the Cortex-A9 which reduces the linefill issuing
925 	  capabilities of the processor.
926 
927 config ARM_ERRATA_643719
928 	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
929 	depends on CPU_V7 && SMP
930 	default y
931 	help
932 	  This option enables the workaround for the 643719 Cortex-A9 (prior to
933 	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
934 	  register returns zero when it should return one. The workaround
935 	  corrects this value, ensuring cache maintenance operations which use
936 	  it behave as intended and avoiding data corruption.
937 
938 config ARM_ERRATA_720789
939 	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
940 	depends on CPU_V7
941 	help
942 	  This option enables the workaround for the 720789 Cortex-A9 (prior to
943 	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
944 	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
945 	  As a consequence of this erratum, some TLB entries which should be
946 	  invalidated are not, resulting in an incoherency in the system page
947 	  tables. The workaround changes the TLB flushing routines to invalidate
948 	  entries regardless of the ASID.
949 
950 config ARM_ERRATA_743622
951 	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
952 	depends on CPU_V7
953 	depends on !ARCH_MULTIPLATFORM
954 	help
955 	  This option enables the workaround for the 743622 Cortex-A9
956 	  (r2p*) erratum. Under very rare conditions, a faulty
957 	  optimisation in the Cortex-A9 Store Buffer may lead to data
958 	  corruption. This workaround sets a specific bit in the diagnostic
959 	  register of the Cortex-A9 which disables the Store Buffer
960 	  optimisation, preventing the defect from occurring. This has no
961 	  visible impact on the overall performance or power consumption of the
962 	  processor.
963 
964 config ARM_ERRATA_751472
965 	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
966 	depends on CPU_V7
967 	depends on !ARCH_MULTIPLATFORM
968 	help
969 	  This option enables the workaround for the 751472 Cortex-A9 (prior
970 	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
971 	  completion of a following broadcasted operation if the second
972 	  operation is received by a CPU before the ICIALLUIS has completed,
973 	  potentially leading to corrupted entries in the cache or TLB.
974 
975 config ARM_ERRATA_754322
976 	bool "ARM errata: possible faulty MMU translations following an ASID switch"
977 	depends on CPU_V7
978 	help
979 	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
980 	  r3p*) erratum. A speculative memory access may cause a page table walk
981 	  which starts prior to an ASID switch but completes afterwards. This
982 	  can populate the micro-TLB with a stale entry which may be hit with
983 	  the new ASID. This workaround places two dsb instructions in the mm
984 	  switching code so that no page table walks can cross the ASID switch.
985 
986 config ARM_ERRATA_754327
987 	bool "ARM errata: no automatic Store Buffer drain"
988 	depends on CPU_V7 && SMP
989 	help
990 	  This option enables the workaround for the 754327 Cortex-A9 (prior to
991 	  r2p0) erratum. The Store Buffer does not have any automatic draining
992 	  mechanism and therefore a livelock may occur if an external agent
993 	  continuously polls a memory location waiting to observe an update.
994 	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
995 	  written polling loops from denying visibility of updates to memory.
996 
997 config ARM_ERRATA_364296
998 	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
999 	depends on CPU_V6
1000 	help
1001 	  This options enables the workaround for the 364296 ARM1136
1002 	  r0p2 erratum (possible cache data corruption with
1003 	  hit-under-miss enabled). It sets the undocumented bit 31 in
1004 	  the auxiliary control register and the FI bit in the control
1005 	  register, thus disabling hit-under-miss without putting the
1006 	  processor into full low interrupt latency mode. ARM11MPCore
1007 	  is not affected.
1008 
1009 config ARM_ERRATA_764369
1010 	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1011 	depends on CPU_V7 && SMP
1012 	help
1013 	  This option enables the workaround for erratum 764369
1014 	  affecting Cortex-A9 MPCore with two or more processors (all
1015 	  current revisions). Under certain timing circumstances, a data
1016 	  cache line maintenance operation by MVA targeting an Inner
1017 	  Shareable memory region may fail to proceed up to either the
1018 	  Point of Coherency or to the Point of Unification of the
1019 	  system. This workaround adds a DSB instruction before the
1020 	  relevant cache maintenance functions and sets a specific bit
1021 	  in the diagnostic control register of the SCU.
1022 
1023 config ARM_ERRATA_775420
1024        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1025        depends on CPU_V7
1026        help
1027 	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1028 	 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
1029 	 operation aborts with MMU exception, it might cause the processor
1030 	 to deadlock. This workaround puts DSB before executing ISB if
1031 	 an abort may occur on cache maintenance.
1032 
1033 config ARM_ERRATA_798181
1034 	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1035 	depends on CPU_V7 && SMP
1036 	help
1037 	  On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1038 	  adequately shooting down all use of the old entries. This
1039 	  option enables the Linux kernel workaround for this erratum
1040 	  which sends an IPI to the CPUs that are running the same ASID
1041 	  as the one being invalidated.
1042 
1043 config ARM_ERRATA_773022
1044 	bool "ARM errata: incorrect instructions may be executed from loop buffer"
1045 	depends on CPU_V7
1046 	help
1047 	  This option enables the workaround for the 773022 Cortex-A15
1048 	  (up to r0p4) erratum. In certain rare sequences of code, the
1049 	  loop buffer may deliver incorrect instructions. This
1050 	  workaround disables the loop buffer to avoid the erratum.
1051 
1052 config ARM_ERRATA_818325_852422
1053 	bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1054 	depends on CPU_V7
1055 	help
1056 	  This option enables the workaround for:
1057 	  - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1058 	    instruction might deadlock.  Fixed in r0p1.
1059 	  - Cortex-A12 852422: Execution of a sequence of instructions might
1060 	    lead to either a data corruption or a CPU deadlock.  Not fixed in
1061 	    any Cortex-A12 cores yet.
1062 	  This workaround for all both errata involves setting bit[12] of the
1063 	  Feature Register. This bit disables an optimisation applied to a
1064 	  sequence of 2 instructions that use opposing condition codes.
1065 
1066 config ARM_ERRATA_821420
1067 	bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1068 	depends on CPU_V7
1069 	help
1070 	  This option enables the workaround for the 821420 Cortex-A12
1071 	  (all revs) erratum. In very rare timing conditions, a sequence
1072 	  of VMOV to Core registers instructions, for which the second
1073 	  one is in the shadow of a branch or abort, can lead to a
1074 	  deadlock when the VMOV instructions are issued out-of-order.
1075 
1076 config ARM_ERRATA_825619
1077 	bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1078 	depends on CPU_V7
1079 	help
1080 	  This option enables the workaround for the 825619 Cortex-A12
1081 	  (all revs) erratum. Within rare timing constraints, executing a
1082 	  DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1083 	  and Device/Strongly-Ordered loads and stores might cause deadlock
1084 
1085 config ARM_ERRATA_857271
1086 	bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1087 	depends on CPU_V7
1088 	help
1089 	  This option enables the workaround for the 857271 Cortex-A12
1090 	  (all revs) erratum. Under very rare timing conditions, the CPU might
1091 	  hang. The workaround is expected to have a < 1% performance impact.
1092 
1093 config ARM_ERRATA_852421
1094 	bool "ARM errata: A17: DMB ST might fail to create order between stores"
1095 	depends on CPU_V7
1096 	help
1097 	  This option enables the workaround for the 852421 Cortex-A17
1098 	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1099 	  execution of a DMB ST instruction might fail to properly order
1100 	  stores from GroupA and stores from GroupB.
1101 
1102 config ARM_ERRATA_852423
1103 	bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1104 	depends on CPU_V7
1105 	help
1106 	  This option enables the workaround for:
1107 	  - Cortex-A17 852423: Execution of a sequence of instructions might
1108 	    lead to either a data corruption or a CPU deadlock.  Not fixed in
1109 	    any Cortex-A17 cores yet.
1110 	  This is identical to Cortex-A12 erratum 852422.  It is a separate
1111 	  config option from the A12 erratum due to the way errata are checked
1112 	  for and handled.
1113 
1114 config ARM_ERRATA_857272
1115 	bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1116 	depends on CPU_V7
1117 	help
1118 	  This option enables the workaround for the 857272 Cortex-A17 erratum.
1119 	  This erratum is not known to be fixed in any A17 revision.
1120 	  This is identical to Cortex-A12 erratum 857271.  It is a separate
1121 	  config option from the A12 erratum due to the way errata are checked
1122 	  for and handled.
1123 
1124 endmenu
1125 
1126 source "arch/arm/common/Kconfig"
1127 
1128 menu "Bus support"
1129 
1130 config ISA
1131 	bool
1132 	help
1133 	  Find out whether you have ISA slots on your motherboard.  ISA is the
1134 	  name of a bus system, i.e. the way the CPU talks to the other stuff
1135 	  inside your box.  Other bus systems are PCI, EISA, MicroChannel
1136 	  (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1137 	  newer boards don't support it.  If you have ISA, say Y, otherwise N.
1138 
1139 # Select ISA DMA controller support
1140 config ISA_DMA
1141 	bool
1142 	select ISA_DMA_API
1143 
1144 # Select ISA DMA interface
1145 config ISA_DMA_API
1146 	bool
1147 
1148 config PCI_NANOENGINE
1149 	bool "BSE nanoEngine PCI support"
1150 	depends on SA1100_NANOENGINE
1151 	help
1152 	  Enable PCI on the BSE nanoEngine board.
1153 
1154 config ARM_ERRATA_814220
1155 	bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1156 	depends on CPU_V7
1157 	help
1158 	  The v7 ARM states that all cache and branch predictor maintenance
1159 	  operations that do not specify an address execute, relative to
1160 	  each other, in program order.
1161 	  However, because of this erratum, an L2 set/way cache maintenance
1162 	  operation can overtake an L1 set/way cache maintenance operation.
1163 	  This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1164 	  r0p4, r0p5.
1165 
1166 endmenu
1167 
1168 menu "Kernel Features"
1169 
1170 config HAVE_SMP
1171 	bool
1172 	help
1173 	  This option should be selected by machines which have an SMP-
1174 	  capable CPU.
1175 
1176 	  The only effect of this option is to make the SMP-related
1177 	  options available to the user for configuration.
1178 
1179 config SMP
1180 	bool "Symmetric Multi-Processing"
1181 	depends on CPU_V6K || CPU_V7
1182 	depends on GENERIC_CLOCKEVENTS
1183 	depends on HAVE_SMP
1184 	depends on MMU || ARM_MPU
1185 	select IRQ_WORK
1186 	help
1187 	  This enables support for systems with more than one CPU. If you have
1188 	  a system with only one CPU, say N. If you have a system with more
1189 	  than one CPU, say Y.
1190 
1191 	  If you say N here, the kernel will run on uni- and multiprocessor
1192 	  machines, but will use only one CPU of a multiprocessor machine. If
1193 	  you say Y here, the kernel will run on many, but not all,
1194 	  uniprocessor machines. On a uniprocessor machine, the kernel
1195 	  will run faster if you say N here.
1196 
1197 	  See also <file:Documentation/x86/i386/IO-APIC.rst>,
1198 	  <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1199 	  <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1200 
1201 	  If you don't know what to do here, say N.
1202 
1203 config SMP_ON_UP
1204 	bool "Allow booting SMP kernel on uniprocessor systems"
1205 	depends on SMP && !XIP_KERNEL && MMU
1206 	default y
1207 	help
1208 	  SMP kernels contain instructions which fail on non-SMP processors.
1209 	  Enabling this option allows the kernel to modify itself to make
1210 	  these instructions safe.  Disabling it allows about 1K of space
1211 	  savings.
1212 
1213 	  If you don't know what to do here, say Y.
1214 
1215 config ARM_CPU_TOPOLOGY
1216 	bool "Support cpu topology definition"
1217 	depends on SMP && CPU_V7
1218 	default y
1219 	help
1220 	  Support ARM cpu topology definition. The MPIDR register defines
1221 	  affinity between processors which is then used to describe the cpu
1222 	  topology of an ARM System.
1223 
1224 config SCHED_MC
1225 	bool "Multi-core scheduler support"
1226 	depends on ARM_CPU_TOPOLOGY
1227 	help
1228 	  Multi-core scheduler support improves the CPU scheduler's decision
1229 	  making when dealing with multi-core CPU chips at a cost of slightly
1230 	  increased overhead in some places. If unsure say N here.
1231 
1232 config SCHED_SMT
1233 	bool "SMT scheduler support"
1234 	depends on ARM_CPU_TOPOLOGY
1235 	help
1236 	  Improves the CPU scheduler's decision making when dealing with
1237 	  MultiThreading at a cost of slightly increased overhead in some
1238 	  places. If unsure say N here.
1239 
1240 config HAVE_ARM_SCU
1241 	bool
1242 	help
1243 	  This option enables support for the ARM snoop control unit
1244 
1245 config HAVE_ARM_ARCH_TIMER
1246 	bool "Architected timer support"
1247 	depends on CPU_V7
1248 	select ARM_ARCH_TIMER
1249 	help
1250 	  This option enables support for the ARM architected timer
1251 
1252 config HAVE_ARM_TWD
1253 	bool
1254 	help
1255 	  This options enables support for the ARM timer and watchdog unit
1256 
1257 config MCPM
1258 	bool "Multi-Cluster Power Management"
1259 	depends on CPU_V7 && SMP
1260 	help
1261 	  This option provides the common power management infrastructure
1262 	  for (multi-)cluster based systems, such as big.LITTLE based
1263 	  systems.
1264 
1265 config MCPM_QUAD_CLUSTER
1266 	bool
1267 	depends on MCPM
1268 	help
1269 	  To avoid wasting resources unnecessarily, MCPM only supports up
1270 	  to 2 clusters by default.
1271 	  Platforms with 3 or 4 clusters that use MCPM must select this
1272 	  option to allow the additional clusters to be managed.
1273 
1274 config BIG_LITTLE
1275 	bool "big.LITTLE support (Experimental)"
1276 	depends on CPU_V7 && SMP
1277 	select MCPM
1278 	help
1279 	  This option enables support selections for the big.LITTLE
1280 	  system architecture.
1281 
1282 config BL_SWITCHER
1283 	bool "big.LITTLE switcher support"
1284 	depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1285 	select CPU_PM
1286 	help
1287 	  The big.LITTLE "switcher" provides the core functionality to
1288 	  transparently handle transition between a cluster of A15's
1289 	  and a cluster of A7's in a big.LITTLE system.
1290 
1291 config BL_SWITCHER_DUMMY_IF
1292 	tristate "Simple big.LITTLE switcher user interface"
1293 	depends on BL_SWITCHER && DEBUG_KERNEL
1294 	help
1295 	  This is a simple and dummy char dev interface to control
1296 	  the big.LITTLE switcher core code.  It is meant for
1297 	  debugging purposes only.
1298 
1299 choice
1300 	prompt "Memory split"
1301 	depends on MMU
1302 	default VMSPLIT_3G
1303 	help
1304 	  Select the desired split between kernel and user memory.
1305 
1306 	  If you are not absolutely sure what you are doing, leave this
1307 	  option alone!
1308 
1309 	config VMSPLIT_3G
1310 		bool "3G/1G user/kernel split"
1311 	config VMSPLIT_3G_OPT
1312 		depends on !ARM_LPAE
1313 		bool "3G/1G user/kernel split (for full 1G low memory)"
1314 	config VMSPLIT_2G
1315 		bool "2G/2G user/kernel split"
1316 	config VMSPLIT_1G
1317 		bool "1G/3G user/kernel split"
1318 endchoice
1319 
1320 config PAGE_OFFSET
1321 	hex
1322 	default PHYS_OFFSET if !MMU
1323 	default 0x40000000 if VMSPLIT_1G
1324 	default 0x80000000 if VMSPLIT_2G
1325 	default 0xB0000000 if VMSPLIT_3G_OPT
1326 	default 0xC0000000
1327 
1328 config KASAN_SHADOW_OFFSET
1329 	hex
1330 	depends on KASAN
1331 	default 0x1f000000 if PAGE_OFFSET=0x40000000
1332 	default 0x5f000000 if PAGE_OFFSET=0x80000000
1333 	default 0x9f000000 if PAGE_OFFSET=0xC0000000
1334 	default 0x8f000000 if PAGE_OFFSET=0xB0000000
1335 	default 0xffffffff
1336 
1337 config NR_CPUS
1338 	int "Maximum number of CPUs (2-32)"
1339 	range 2 32
1340 	depends on SMP
1341 	default "4"
1342 
1343 config HOTPLUG_CPU
1344 	bool "Support for hot-pluggable CPUs"
1345 	depends on SMP
1346 	select GENERIC_IRQ_MIGRATION
1347 	help
1348 	  Say Y here to experiment with turning CPUs off and on.  CPUs
1349 	  can be controlled through /sys/devices/system/cpu.
1350 
1351 config ARM_PSCI
1352 	bool "Support for the ARM Power State Coordination Interface (PSCI)"
1353 	depends on HAVE_ARM_SMCCC
1354 	select ARM_PSCI_FW
1355 	help
1356 	  Say Y here if you want Linux to communicate with system firmware
1357 	  implementing the PSCI specification for CPU-centric power
1358 	  management operations described in ARM document number ARM DEN
1359 	  0022A ("Power State Coordination Interface System Software on
1360 	  ARM processors").
1361 
1362 # The GPIO number here must be sorted by descending number. In case of
1363 # a multiplatform kernel, we just want the highest value required by the
1364 # selected platforms.
1365 config ARCH_NR_GPIO
1366 	int
1367 	default 2048 if ARCH_SOCFPGA
1368 	default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1369 		ARCH_ZYNQ || ARCH_ASPEED
1370 	default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1371 		SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1372 	default 416 if ARCH_SUNXI
1373 	default 392 if ARCH_U8500
1374 	default 352 if ARCH_VT8500
1375 	default 288 if ARCH_ROCKCHIP
1376 	default 264 if MACH_H4700
1377 	default 0
1378 	help
1379 	  Maximum number of GPIOs in the system.
1380 
1381 	  If unsure, leave the default value.
1382 
1383 config HZ_FIXED
1384 	int
1385 	default 200 if ARCH_EBSA110
1386 	default 128 if SOC_AT91RM9200
1387 	default 0
1388 
1389 choice
1390 	depends on HZ_FIXED = 0
1391 	prompt "Timer frequency"
1392 
1393 config HZ_100
1394 	bool "100 Hz"
1395 
1396 config HZ_200
1397 	bool "200 Hz"
1398 
1399 config HZ_250
1400 	bool "250 Hz"
1401 
1402 config HZ_300
1403 	bool "300 Hz"
1404 
1405 config HZ_500
1406 	bool "500 Hz"
1407 
1408 config HZ_1000
1409 	bool "1000 Hz"
1410 
1411 endchoice
1412 
1413 config HZ
1414 	int
1415 	default HZ_FIXED if HZ_FIXED != 0
1416 	default 100 if HZ_100
1417 	default 200 if HZ_200
1418 	default 250 if HZ_250
1419 	default 300 if HZ_300
1420 	default 500 if HZ_500
1421 	default 1000
1422 
1423 config SCHED_HRTICK
1424 	def_bool HIGH_RES_TIMERS
1425 
1426 config THUMB2_KERNEL
1427 	bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1428 	depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1429 	default y if CPU_THUMBONLY
1430 	select ARM_UNWIND
1431 	help
1432 	  By enabling this option, the kernel will be compiled in
1433 	  Thumb-2 mode.
1434 
1435 	  If unsure, say N.
1436 
1437 config ARM_PATCH_IDIV
1438 	bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1439 	depends on CPU_32v7 && !XIP_KERNEL
1440 	default y
1441 	help
1442 	  The ARM compiler inserts calls to __aeabi_idiv() and
1443 	  __aeabi_uidiv() when it needs to perform division on signed
1444 	  and unsigned integers. Some v7 CPUs have support for the sdiv
1445 	  and udiv instructions that can be used to implement those
1446 	  functions.
1447 
1448 	  Enabling this option allows the kernel to modify itself to
1449 	  replace the first two instructions of these library functions
1450 	  with the sdiv or udiv plus "bx lr" instructions when the CPU
1451 	  it is running on supports them. Typically this will be faster
1452 	  and less power intensive than running the original library
1453 	  code to do integer division.
1454 
1455 config AEABI
1456 	bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1457 		!CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1458 	default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1459 	help
1460 	  This option allows for the kernel to be compiled using the latest
1461 	  ARM ABI (aka EABI).  This is only useful if you are using a user
1462 	  space environment that is also compiled with EABI.
1463 
1464 	  Since there are major incompatibilities between the legacy ABI and
1465 	  EABI, especially with regard to structure member alignment, this
1466 	  option also changes the kernel syscall calling convention to
1467 	  disambiguate both ABIs and allow for backward compatibility support
1468 	  (selected with CONFIG_OABI_COMPAT).
1469 
1470 	  To use this you need GCC version 4.0.0 or later.
1471 
1472 config OABI_COMPAT
1473 	bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1474 	depends on AEABI && !THUMB2_KERNEL
1475 	help
1476 	  This option preserves the old syscall interface along with the
1477 	  new (ARM EABI) one. It also provides a compatibility layer to
1478 	  intercept syscalls that have structure arguments which layout
1479 	  in memory differs between the legacy ABI and the new ARM EABI
1480 	  (only for non "thumb" binaries). This option adds a tiny
1481 	  overhead to all syscalls and produces a slightly larger kernel.
1482 
1483 	  The seccomp filter system will not be available when this is
1484 	  selected, since there is no way yet to sensibly distinguish
1485 	  between calling conventions during filtering.
1486 
1487 	  If you know you'll be using only pure EABI user space then you
1488 	  can say N here. If this option is not selected and you attempt
1489 	  to execute a legacy ABI binary then the result will be
1490 	  UNPREDICTABLE (in fact it can be predicted that it won't work
1491 	  at all). If in doubt say N.
1492 
1493 config ARCH_SELECT_MEMORY_MODEL
1494 	bool
1495 
1496 config ARCH_FLATMEM_ENABLE
1497 	bool
1498 
1499 config ARCH_SPARSEMEM_ENABLE
1500 	bool
1501 	select SPARSEMEM_STATIC if SPARSEMEM
1502 
1503 config HAVE_ARCH_PFN_VALID
1504 	def_bool y
1505 
1506 config HIGHMEM
1507 	bool "High Memory Support"
1508 	depends on MMU
1509 	help
1510 	  The address space of ARM processors is only 4 Gigabytes large
1511 	  and it has to accommodate user address space, kernel address
1512 	  space as well as some memory mapped IO. That means that, if you
1513 	  have a large amount of physical memory and/or IO, not all of the
1514 	  memory can be "permanently mapped" by the kernel. The physical
1515 	  memory that is not permanently mapped is called "high memory".
1516 
1517 	  Depending on the selected kernel/user memory split, minimum
1518 	  vmalloc space and actual amount of RAM, you may not need this
1519 	  option which should result in a slightly faster kernel.
1520 
1521 	  If unsure, say n.
1522 
1523 config HIGHPTE
1524 	bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1525 	depends on HIGHMEM
1526 	default y
1527 	help
1528 	  The VM uses one page of physical memory for each page table.
1529 	  For systems with a lot of processes, this can use a lot of
1530 	  precious low memory, eventually leading to low memory being
1531 	  consumed by page tables.  Setting this option will allow
1532 	  user-space 2nd level page tables to reside in high memory.
1533 
1534 config CPU_SW_DOMAIN_PAN
1535 	bool "Enable use of CPU domains to implement privileged no-access"
1536 	depends on MMU && !ARM_LPAE
1537 	default y
1538 	help
1539 	  Increase kernel security by ensuring that normal kernel accesses
1540 	  are unable to access userspace addresses.  This can help prevent
1541 	  use-after-free bugs becoming an exploitable privilege escalation
1542 	  by ensuring that magic values (such as LIST_POISON) will always
1543 	  fault when dereferenced.
1544 
1545 	  CPUs with low-vector mappings use a best-efforts implementation.
1546 	  Their lower 1MB needs to remain accessible for the vectors, but
1547 	  the remainder of userspace will become appropriately inaccessible.
1548 
1549 config HW_PERF_EVENTS
1550 	def_bool y
1551 	depends on ARM_PMU
1552 
1553 config SYS_SUPPORTS_HUGETLBFS
1554        def_bool y
1555        depends on ARM_LPAE
1556 
1557 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1558        def_bool y
1559        depends on ARM_LPAE
1560 
1561 config ARCH_WANT_GENERAL_HUGETLB
1562 	def_bool y
1563 
1564 config ARM_MODULE_PLTS
1565 	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1566 	depends on MODULES
1567 	default y
1568 	help
1569 	  Allocate PLTs when loading modules so that jumps and calls whose
1570 	  targets are too far away for their relative offsets to be encoded
1571 	  in the instructions themselves can be bounced via veneers in the
1572 	  module's PLT. This allows modules to be allocated in the generic
1573 	  vmalloc area after the dedicated module memory area has been
1574 	  exhausted. The modules will use slightly more memory, but after
1575 	  rounding up to page size, the actual memory footprint is usually
1576 	  the same.
1577 
1578 	  Disabling this is usually safe for small single-platform
1579 	  configurations. If unsure, say y.
1580 
1581 config FORCE_MAX_ZONEORDER
1582 	int "Maximum zone order"
1583 	default "12" if SOC_AM33XX
1584 	default "9" if SA1111 || ARCH_EFM32
1585 	default "11"
1586 	help
1587 	  The kernel memory allocator divides physically contiguous memory
1588 	  blocks into "zones", where each zone is a power of two number of
1589 	  pages.  This option selects the largest power of two that the kernel
1590 	  keeps in the memory allocator.  If you need to allocate very large
1591 	  blocks of physically contiguous memory, then you may need to
1592 	  increase this value.
1593 
1594 	  This config option is actually maximum order plus one. For example,
1595 	  a value of 11 means that the largest free memory block is 2^10 pages.
1596 
1597 config ALIGNMENT_TRAP
1598 	bool
1599 	depends on CPU_CP15_MMU
1600 	default y if !ARCH_EBSA110
1601 	select HAVE_PROC_CPU if PROC_FS
1602 	help
1603 	  ARM processors cannot fetch/store information which is not
1604 	  naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1605 	  address divisible by 4. On 32-bit ARM processors, these non-aligned
1606 	  fetch/store instructions will be emulated in software if you say
1607 	  here, which has a severe performance impact. This is necessary for
1608 	  correct operation of some network protocols. With an IP-only
1609 	  configuration it is safe to say N, otherwise say Y.
1610 
1611 config UACCESS_WITH_MEMCPY
1612 	bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1613 	depends on MMU
1614 	default y if CPU_FEROCEON
1615 	help
1616 	  Implement faster copy_to_user and clear_user methods for CPU
1617 	  cores where a 8-word STM instruction give significantly higher
1618 	  memory write throughput than a sequence of individual 32bit stores.
1619 
1620 	  A possible side effect is a slight increase in scheduling latency
1621 	  between threads sharing the same address space if they invoke
1622 	  such copy operations with large buffers.
1623 
1624 	  However, if the CPU data cache is using a write-allocate mode,
1625 	  this option is unlikely to provide any performance gain.
1626 
1627 config PARAVIRT
1628 	bool "Enable paravirtualization code"
1629 	help
1630 	  This changes the kernel so it can modify itself when it is run
1631 	  under a hypervisor, potentially improving performance significantly
1632 	  over full virtualization.
1633 
1634 config PARAVIRT_TIME_ACCOUNTING
1635 	bool "Paravirtual steal time accounting"
1636 	select PARAVIRT
1637 	help
1638 	  Select this option to enable fine granularity task steal time
1639 	  accounting. Time spent executing other tasks in parallel with
1640 	  the current vCPU is discounted from the vCPU power. To account for
1641 	  that, there can be a small performance impact.
1642 
1643 	  If in doubt, say N here.
1644 
1645 config XEN_DOM0
1646 	def_bool y
1647 	depends on XEN
1648 
1649 config XEN
1650 	bool "Xen guest support on ARM"
1651 	depends on ARM && AEABI && OF
1652 	depends on CPU_V7 && !CPU_V6
1653 	depends on !GENERIC_ATOMIC64
1654 	depends on MMU
1655 	select ARCH_DMA_ADDR_T_64BIT
1656 	select ARM_PSCI
1657 	select SWIOTLB
1658 	select SWIOTLB_XEN
1659 	select PARAVIRT
1660 	help
1661 	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1662 
1663 config STACKPROTECTOR_PER_TASK
1664 	bool "Use a unique stack canary value for each task"
1665 	depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1666 	select GCC_PLUGIN_ARM_SSP_PER_TASK
1667 	default y
1668 	help
1669 	  Due to the fact that GCC uses an ordinary symbol reference from
1670 	  which to load the value of the stack canary, this value can only
1671 	  change at reboot time on SMP systems, and all tasks running in the
1672 	  kernel's address space are forced to use the same canary value for
1673 	  the entire duration that the system is up.
1674 
1675 	  Enable this option to switch to a different method that uses a
1676 	  different canary value for each task.
1677 
1678 config RELOCATABLE
1679 	bool
1680 	depends on !XIP_KERNEL && !JUMP_LABEL
1681 	select HAVE_ARCH_PREL32_RELOCATIONS
1682 
1683 config RANDOMIZE_BASE
1684 	bool "Randomize the address of the kernel image"
1685 	depends on MMU && AUTO_ZRELADDR
1686 	depends on !XIP_KERNEL && !ZBOOT_ROM && !JUMP_LABEL
1687 	select RELOCATABLE
1688 	select ARM_MODULE_PLTS if MODULES
1689 	select MODULE_REL_CRCS if MODVERSIONS
1690 	help
1691 	  Randomizes the virtual and physical address at which the kernel
1692 	  image is loaded, as a security feature that deters exploit attempts
1693 	  relying on knowledge of the location of kernel internals.
1694 
1695 endmenu
1696 
1697 menu "Boot options"
1698 
1699 config USE_OF
1700 	bool "Flattened Device Tree support"
1701 	select IRQ_DOMAIN
1702 	select OF
1703 	help
1704 	  Include support for flattened device tree machine descriptions.
1705 
1706 config ATAGS
1707 	bool "Support for the traditional ATAGS boot data passing" if USE_OF
1708 	default y
1709 	help
1710 	  This is the traditional way of passing data to the kernel at boot
1711 	  time. If you are solely relying on the flattened device tree (or
1712 	  the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1713 	  to remove ATAGS support from your kernel binary.  If unsure,
1714 	  leave this to y.
1715 
1716 config DEPRECATED_PARAM_STRUCT
1717 	bool "Provide old way to pass kernel parameters"
1718 	depends on ATAGS
1719 	help
1720 	  This was deprecated in 2001 and announced to live on for 5 years.
1721 	  Some old boot loaders still use this way.
1722 
1723 # Compressed boot loader in ROM.  Yes, we really want to ask about
1724 # TEXT and BSS so we preserve their values in the config files.
1725 config ZBOOT_ROM_TEXT
1726 	hex "Compressed ROM boot loader base address"
1727 	default 0x0
1728 	help
1729 	  The physical address at which the ROM-able zImage is to be
1730 	  placed in the target.  Platforms which normally make use of
1731 	  ROM-able zImage formats normally set this to a suitable
1732 	  value in their defconfig file.
1733 
1734 	  If ZBOOT_ROM is not enabled, this has no effect.
1735 
1736 config ZBOOT_ROM_BSS
1737 	hex "Compressed ROM boot loader BSS address"
1738 	default 0x0
1739 	help
1740 	  The base address of an area of read/write memory in the target
1741 	  for the ROM-able zImage which must be available while the
1742 	  decompressor is running. It must be large enough to hold the
1743 	  entire decompressed kernel plus an additional 128 KiB.
1744 	  Platforms which normally make use of ROM-able zImage formats
1745 	  normally set this to a suitable value in their defconfig file.
1746 
1747 	  If ZBOOT_ROM is not enabled, this has no effect.
1748 
1749 config ZBOOT_ROM
1750 	bool "Compressed boot loader in ROM/flash"
1751 	depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1752 	depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1753 	help
1754 	  Say Y here if you intend to execute your compressed kernel image
1755 	  (zImage) directly from ROM or flash.  If unsure, say N.
1756 
1757 config ARM_APPENDED_DTB
1758 	bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1759 	depends on OF
1760 	help
1761 	  With this option, the boot code will look for a device tree binary
1762 	  (DTB) appended to zImage
1763 	  (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1764 
1765 	  This is meant as a backward compatibility convenience for those
1766 	  systems with a bootloader that can't be upgraded to accommodate
1767 	  the documented boot protocol using a device tree.
1768 
1769 	  Beware that there is very little in terms of protection against
1770 	  this option being confused by leftover garbage in memory that might
1771 	  look like a DTB header after a reboot if no actual DTB is appended
1772 	  to zImage.  Do not leave this option active in a production kernel
1773 	  if you don't intend to always append a DTB.  Proper passing of the
1774 	  location into r2 of a bootloader provided DTB is always preferable
1775 	  to this option.
1776 
1777 config ARM_ATAG_DTB_COMPAT
1778 	bool "Supplement the appended DTB with traditional ATAG information"
1779 	depends on ARM_APPENDED_DTB
1780 	help
1781 	  Some old bootloaders can't be updated to a DTB capable one, yet
1782 	  they provide ATAGs with memory configuration, the ramdisk address,
1783 	  the kernel cmdline string, etc.  Such information is dynamically
1784 	  provided by the bootloader and can't always be stored in a static
1785 	  DTB.  To allow a device tree enabled kernel to be used with such
1786 	  bootloaders, this option allows zImage to extract the information
1787 	  from the ATAG list and store it at run time into the appended DTB.
1788 
1789 choice
1790 	prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1791 	default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1792 
1793 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1794 	bool "Use bootloader kernel arguments if available"
1795 	help
1796 	  Uses the command-line options passed by the boot loader instead of
1797 	  the device tree bootargs property. If the boot loader doesn't provide
1798 	  any, the device tree bootargs property will be used.
1799 
1800 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1801 	bool "Extend with bootloader kernel arguments"
1802 	help
1803 	  The command-line arguments provided by the boot loader will be
1804 	  appended to the the device tree bootargs property.
1805 
1806 endchoice
1807 
1808 config CMDLINE
1809 	string "Default kernel command string"
1810 	default ""
1811 	help
1812 	  On some architectures (EBSA110 and CATS), there is currently no way
1813 	  for the boot loader to pass arguments to the kernel. For these
1814 	  architectures, you should supply some command-line options at build
1815 	  time by entering them here. As a minimum, you should specify the
1816 	  memory size and the root device (e.g., mem=64M root=/dev/nfs).
1817 
1818 choice
1819 	prompt "Kernel command line type" if CMDLINE != ""
1820 	default CMDLINE_FROM_BOOTLOADER
1821 
1822 config CMDLINE_FROM_BOOTLOADER
1823 	bool "Use bootloader kernel arguments if available"
1824 	help
1825 	  Uses the command-line options passed by the boot loader. If
1826 	  the boot loader doesn't provide any, the default kernel command
1827 	  string provided in CMDLINE will be used.
1828 
1829 config CMDLINE_EXTEND
1830 	bool "Extend bootloader kernel arguments"
1831 	help
1832 	  The command-line arguments provided by the boot loader will be
1833 	  appended to the default kernel command string.
1834 
1835 config CMDLINE_FORCE
1836 	bool "Always use the default kernel command string"
1837 	help
1838 	  Always use the default kernel command string, even if the boot
1839 	  loader passes other arguments to the kernel.
1840 	  This is useful if you cannot or don't want to change the
1841 	  command-line options your boot loader passes to the kernel.
1842 endchoice
1843 
1844 config XIP_KERNEL
1845 	bool "Kernel Execute-In-Place from ROM"
1846 	depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1847 	help
1848 	  Execute-In-Place allows the kernel to run from non-volatile storage
1849 	  directly addressable by the CPU, such as NOR flash. This saves RAM
1850 	  space since the text section of the kernel is not loaded from flash
1851 	  to RAM.  Read-write sections, such as the data section and stack,
1852 	  are still copied to RAM.  The XIP kernel is not compressed since
1853 	  it has to run directly from flash, so it will take more space to
1854 	  store it.  The flash address used to link the kernel object files,
1855 	  and for storing it, is configuration dependent. Therefore, if you
1856 	  say Y here, you must know the proper physical address where to
1857 	  store the kernel image depending on your own flash memory usage.
1858 
1859 	  Also note that the make target becomes "make xipImage" rather than
1860 	  "make zImage" or "make Image".  The final kernel binary to put in
1861 	  ROM memory will be arch/arm/boot/xipImage.
1862 
1863 	  If unsure, say N.
1864 
1865 config XIP_PHYS_ADDR
1866 	hex "XIP Kernel Physical Location"
1867 	depends on XIP_KERNEL
1868 	default "0x00080000"
1869 	help
1870 	  This is the physical address in your flash memory the kernel will
1871 	  be linked for and stored to.  This address is dependent on your
1872 	  own flash usage.
1873 
1874 config XIP_DEFLATED_DATA
1875 	bool "Store kernel .data section compressed in ROM"
1876 	depends on XIP_KERNEL
1877 	select ZLIB_INFLATE
1878 	help
1879 	  Before the kernel is actually executed, its .data section has to be
1880 	  copied to RAM from ROM. This option allows for storing that data
1881 	  in compressed form and decompressed to RAM rather than merely being
1882 	  copied, saving some precious ROM space. A possible drawback is a
1883 	  slightly longer boot delay.
1884 
1885 config KEXEC
1886 	bool "Kexec system call (EXPERIMENTAL)"
1887 	depends on (!SMP || PM_SLEEP_SMP)
1888 	depends on MMU
1889 	select KEXEC_CORE
1890 	help
1891 	  kexec is a system call that implements the ability to shutdown your
1892 	  current kernel, and to start another kernel.  It is like a reboot
1893 	  but it is independent of the system firmware.   And like a reboot
1894 	  you can start any kernel with it, not just Linux.
1895 
1896 	  It is an ongoing process to be certain the hardware in a machine
1897 	  is properly shutdown, so do not be surprised if this code does not
1898 	  initially work for you.
1899 
1900 config ATAGS_PROC
1901 	bool "Export atags in procfs"
1902 	depends on ATAGS && KEXEC
1903 	default y
1904 	help
1905 	  Should the atags used to boot the kernel be exported in an "atags"
1906 	  file in procfs. Useful with kexec.
1907 
1908 config CRASH_DUMP
1909 	bool "Build kdump crash kernel (EXPERIMENTAL)"
1910 	help
1911 	  Generate crash dump after being started by kexec. This should
1912 	  be normally only set in special crash dump kernels which are
1913 	  loaded in the main kernel with kexec-tools into a specially
1914 	  reserved region and then later executed after a crash by
1915 	  kdump/kexec. The crash dump kernel must be compiled to a
1916 	  memory address not used by the main kernel
1917 
1918 	  For more details see Documentation/admin-guide/kdump/kdump.rst
1919 
1920 config AUTO_ZRELADDR
1921 	bool "Auto calculation of the decompressed kernel image address"
1922 	help
1923 	  ZRELADDR is the physical address where the decompressed kernel
1924 	  image will be placed. If AUTO_ZRELADDR is selected, the address
1925 	  will be determined at run-time by masking the current IP with
1926 	  0xf8000000. This assumes the zImage being placed in the first 128MB
1927 	  from start of memory.
1928 
1929 config EFI_STUB
1930 	bool
1931 
1932 config EFI
1933 	bool "UEFI runtime support"
1934 	depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1935 	select UCS2_STRING
1936 	select EFI_PARAMS_FROM_FDT
1937 	select EFI_STUB
1938 	select EFI_GENERIC_STUB
1939 	select EFI_RUNTIME_WRAPPERS
1940 	help
1941 	  This option provides support for runtime services provided
1942 	  by UEFI firmware (such as non-volatile variables, realtime
1943 	  clock, and platform reset). A UEFI stub is also provided to
1944 	  allow the kernel to be booted as an EFI application. This
1945 	  is only useful for kernels that may run on systems that have
1946 	  UEFI firmware.
1947 
1948 config DMI
1949 	bool "Enable support for SMBIOS (DMI) tables"
1950 	depends on EFI
1951 	default y
1952 	help
1953 	  This enables SMBIOS/DMI feature for systems.
1954 
1955 	  This option is only useful on systems that have UEFI firmware.
1956 	  However, even with this option, the resultant kernel should
1957 	  continue to boot on existing non-UEFI platforms.
1958 
1959 	  NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1960 	  i.e., the the practice of identifying the platform via DMI to
1961 	  decide whether certain workarounds for buggy hardware and/or
1962 	  firmware need to be enabled. This would require the DMI subsystem
1963 	  to be enabled much earlier than we do on ARM, which is non-trivial.
1964 
1965 endmenu
1966 
1967 menu "CPU Power Management"
1968 
1969 source "drivers/cpufreq/Kconfig"
1970 
1971 source "drivers/cpuidle/Kconfig"
1972 
1973 endmenu
1974 
1975 menu "Floating point emulation"
1976 
1977 comment "At least one emulation must be selected"
1978 
1979 config FPE_NWFPE
1980 	bool "NWFPE math emulation"
1981 	depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1982 	help
1983 	  Say Y to include the NWFPE floating point emulator in the kernel.
1984 	  This is necessary to run most binaries. Linux does not currently
1985 	  support floating point hardware so you need to say Y here even if
1986 	  your machine has an FPA or floating point co-processor podule.
1987 
1988 	  You may say N here if you are going to load the Acorn FPEmulator
1989 	  early in the bootup.
1990 
1991 config FPE_NWFPE_XP
1992 	bool "Support extended precision"
1993 	depends on FPE_NWFPE
1994 	help
1995 	  Say Y to include 80-bit support in the kernel floating-point
1996 	  emulator.  Otherwise, only 32 and 64-bit support is compiled in.
1997 	  Note that gcc does not generate 80-bit operations by default,
1998 	  so in most cases this option only enlarges the size of the
1999 	  floating point emulator without any good reason.
2000 
2001 	  You almost surely want to say N here.
2002 
2003 config FPE_FASTFPE
2004 	bool "FastFPE math emulation (EXPERIMENTAL)"
2005 	depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2006 	help
2007 	  Say Y here to include the FAST floating point emulator in the kernel.
2008 	  This is an experimental much faster emulator which now also has full
2009 	  precision for the mantissa.  It does not support any exceptions.
2010 	  It is very simple, and approximately 3-6 times faster than NWFPE.
2011 
2012 	  It should be sufficient for most programs.  It may be not suitable
2013 	  for scientific calculations, but you have to check this for yourself.
2014 	  If you do not feel you need a faster FP emulation you should better
2015 	  choose NWFPE.
2016 
2017 config VFP
2018 	bool "VFP-format floating point maths"
2019 	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2020 	help
2021 	  Say Y to include VFP support code in the kernel. This is needed
2022 	  if your hardware includes a VFP unit.
2023 
2024 	  Please see <file:Documentation/arm/vfp/release-notes.rst> for
2025 	  release notes and additional status information.
2026 
2027 	  Say N if your target does not have VFP hardware.
2028 
2029 config VFPv3
2030 	bool
2031 	depends on VFP
2032 	default y if CPU_V7
2033 
2034 config NEON
2035 	bool "Advanced SIMD (NEON) Extension support"
2036 	depends on VFPv3 && CPU_V7
2037 	help
2038 	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2039 	  Extension.
2040 
2041 config KERNEL_MODE_NEON
2042 	bool "Support for NEON in kernel mode"
2043 	depends on NEON && AEABI
2044 	help
2045 	  Say Y to include support for NEON in kernel mode.
2046 
2047 endmenu
2048 
2049 menu "Power management options"
2050 
2051 source "kernel/power/Kconfig"
2052 
2053 config ARCH_SUSPEND_POSSIBLE
2054 	depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2055 		CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2056 	def_bool y
2057 
2058 config ARM_CPU_SUSPEND
2059 	def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2060 	depends on ARCH_SUSPEND_POSSIBLE
2061 
2062 config ARCH_HIBERNATION_POSSIBLE
2063 	bool
2064 	depends on MMU
2065 	default y if ARCH_SUSPEND_POSSIBLE
2066 
2067 endmenu
2068 
2069 source "drivers/firmware/Kconfig"
2070 
2071 if CRYPTO
2072 source "arch/arm/crypto/Kconfig"
2073 endif
2074 
2075 source "arch/arm/Kconfig.assembler"
2076