1/* 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 12 * of conditions and the following disclaimer in the documentation and/or other materials 13 * provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include "arch_config.h" 33 34 .equ MPIDR_CPUID_MASK, 0xffU 35 36 .extern g_saveAR 37 .extern g_saveSRContext 38 39 .global OsSRSaveRegister 40 .global OsSRRestoreRegister 41 42 .fpu vfpv4 43 @.fpu neon 44 .arch armv7a 45 46 .text 47 48OsSRSaveRegister: 49 PUSH {R2} 50 LDR R2, =g_saveAR 51 STR R0, [R2] 52 STR R1, [R2, #4] 53 POP {R2} 54 55 MRC P15, 0, R0, c0, c0, 5 56 AND R0, R0, #MPIDR_CPUID_MASK 57 MOV R1, #72 @This number is the total number of bytes in the task context register(R0~R15, SPSR, CPSR). 58 MUL R1, R1, R0 59 60 LDR R0, =g_saveSRContext 61 ADD R0, R0, R1 62 ADD R0, R0, #72 63 64 MOV R1, SP 65 STMFD R0!, {R1} 66 67 MRS R1, SPSR 68 STMFD R0!, {R1} 69 70 MOV R1, LR 71 STMFD R0!, {R1} @PC 72 STMFD R0!, {R1} @LR 73 74 STMFD R0!, {R12} 75 76 MOV R12, R0 77 78 LDR R0, =g_saveAR 79 LDR R0, [R0] 80 LDR R1, =g_saveAR 81 LDR R1, [R1, #4] 82 83 STMFD R12!, {R0-R3} 84 STMFD R12!, {R4-R11} 85 86 MRS R0, CPSR 87 STMFD R12!, {R0} 88 89 BX LR 90 91OsSRRestoreRegister: 92 MRC P15, 0, R0, c0, c0, 5 93 AND R0, R0, #MPIDR_CPUID_MASK 94 MOV R1, #72 @This number is the total number of bytes in the task context register(R0~R15, SPSR, CPSR). 95 MUL R1, R1, R0 96 97 LDR R12, =g_saveSRContext 98 ADD R12, R12, R1 99 100 LDMFD R12!, {R0} 101 MSR CPSR_cxsf, R0 102 103 LDMFD R12!, {R4-R11} 104 LDMFD R12!, {R0-R3} 105 106 PUSH {R2} 107 LDR R2, =g_saveAR 108 STR R0, [R2] 109 STR R1, [R2, #4] 110 POP {R2} 111 112 MOV R0, R12 113 LDMFD R0!, {R12} 114 LDMFD R0!, {R1} @LR 115 LDMFD R0!, {R1} @PC 116 117 MOV LR, R1 118 119 LDMFD R0!, {R1} 120 MSR SPSR_cxsf, R1 121 122 LDMFD R0!, {R1} 123 MOV SP, R1 124 125 LDR R0, =g_saveAR 126 LDR R0, [R0] 127 LDR R1, =g_saveAR 128 LDR R1, [R1, #4] 129 130 BX LR 131 132 .end 133