Lines Matching refs:invalidate
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
149 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
157 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
177 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
178 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
180 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
181 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
217 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
237 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
242 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
256 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
280 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
347 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
475 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
479 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
519 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
520 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
533 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
536 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4